Microparallel Processor Bidding Model for Register Allocation
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Solution Overview
Problem
Conventional parallelism in computer systems is difficult for programmers to implement effectively, and existing technologies like superscalar, EPIC, and VLIW architectures are inefficient in exploiting fine-grained microparallelism opportunities due to lack of suitable hardware support, limiting the ability to parallelize short to intermediate stretches of code.
Innovation Solution
A computer-implemented method using a bidding model to allocate additional registers and execution units dynamically for identified stretches of code, allowing compilers and assembler language coders to implement microparallelization by inserting specific instructions like PushAndBidForParallelExecution and PopAndReleaseParallelExecution, enabling variable parallelism and correct program execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional parallelism techniques (superscalar, EPIC, VLIW) are used, then processor performance is improved, but the ability to exploit fine-grained microparallelism in short to intermediate code stretches is limited due to lack of suitable hardware support
Solution Approach 1:
The patent implements dynamic allocation of paired units (execution units with associated register half-sets) that can be temporarily assigned to parallelize short to intermediate code stretches. The compiler inserts bidding instructions that request paired units at runtime, and the hardware dynamically grants or denies these requests based on availability. This dynamic mechanism enables microparallelism exploitation without fixed architectural constraints, resolving the contradiction between conventional parallelism performance and adaptability to fine-grained parallelism opportunities.
2Adaptability or versatility
If additional paired units are allocated for parallel execution, then microparallelism capabilities are enhanced, but device complexity increases due to additional registers and execution units
Solution Approach 1:
The patent segments the processor resources into multiple paired units, where each paired unit consists of an execution unit and an associated half-set of registers. This segmentation allows independent allocation and management of parallel execution resources. By dividing the processor state into separable paired units, the system can allocate only the necessary number of units for each parallelization opportunity, enhancing microparallelism capabilities while managing complexity through modular resource organization.
Solution Approach 2:
The patent implements a bidding mechanism where paired units are temporarily allocated for the duration of parallel code execution and then released back to the pool of available units. The compiler inserts bidding instructions at the start of parallel stretches and corresponding release instructions at the end. This temporary allocation and recovery approach allows the system to enhance microparallelism capabilities when needed while returning to the baseline configuration when parallelism is not required, effectively managing device complexity.
3Productivity
If a bidding model is implemented to dynamically allocate paired units, then parallel execution efficiency is improved, but the difficulty of detecting and measuring parallelization opportunities increases
Solution Approach 1:
The patent employs a compiler-based approach where parallelization opportunities are detected and marked during the compilation phase. The compiler analyzes the source code, identifies stretches suitable for microparallelism, and inserts bidding instructions at the beginning of these stretches along with synchronization instructions at the end. This preliminary action transfers the complexity of detecting parallelization opportunities from runtime to compiletime, allowing the runtime bidding mechanism to focus solely on allocating resources based on pre-identified opportunities, thereby improving parallel execution efficiency while managing detection complexity.
Data Source
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AI summary
An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus. The enhanced mechanism enables a variable amount of parallelism to be implemented and yet provides correct program execution even if less parallelism is available than ideal for a given computer program.