Integrated Microphone Bias Circuit With IC High-Pass Filtering

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Solution Overview

Problem

Conventional microphone circuits require a large layout space due to the separation of biasing circuits from integrated circuits, which is not suitable for portable devices with limited size requirements, as capacitors with high enough capacitance for proper frequency filtering cannot be integrated into semiconductor manufacturing processes.

Innovation Solution

The biasing circuit is merged into the integrated circuit, utilizing a capacitor with a capacitance ranging from 1 fF to 100 pF and a resistor with a resistance greater than 1 MΩ, implemented using diodes or transistors to achieve a high pass filter with a cutoff frequency greater than 20 Hz, allowing for a compact microphone circuit design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the biasing circuit is separated from the integrated circuit, then the high pass filter cutoff frequency can be maintained above 20 Hz, but the layout space occupied by the microphone circuit increases

Engineering Contradiction:
Improvehigh pass filter cutoff frequencyVSAvoidlayout space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the biasing circuit with the integrated circuit into a single integrated structure. The biasing circuit includes a capacitor coupled between the microphone output node and ground, and a resistor coupled between the capacitor node and a second voltage source, all integrated on the same semiconductor substrate as the operational amplifier and other circuit elements. This integration eliminates the need for separate discrete components while maintaining the high pass filter characteristics with cutoff frequency above 20 Hz.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If a capacitor with capacitance greater than 0.1 μF is used to maintain cutoff frequency above 20 Hz, then the high pass filter performance is improved, but the capacitor cannot be merged into the integrated circuit

Engineering Contradiction:
Improvehigh pass filter cutoff frequencyVSAvoidintegrated circuit fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the parameter values to be compatible with integrated circuit fabrication capabilities. Instead of requiring a capacitor with capacitance greater than 0.1 μF, the design uses a capacitor with capacitance between 1 fF and 100 pF. To compensate and maintain the cutoff frequency above 20 Hz, the resistor value is increased to greater than 1 MΩ. This parameter adjustment allows the high pass filter to function correctly while using only standard integrated circuit component values.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/discrete capacitor component with an integrated circuit capacitor implemented through standard semiconductor fabrication processes. The capacitor is formed using standard IC capacitor structures (such as MIM capacitors or diffusion capacitors) that can be created during the same fabrication process as the operational amplifier and other circuit elements, eliminating the need for separate discrete capacitor components.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Area of stationary object

If the biasing circuit is integrated into the integrated circuit, then the layout space is reduced, but conventional semiconductor manufacturing processes cannot form capacitors with sufficient capacitance

Engineering Contradiction:
Improvelayout spaceVSAvoidhigh pass filter cutoff frequency
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces a second voltage source as an intermediary element in the biasing circuit. The resistor is coupled between the capacitor node and this second voltage source rather than directly to ground or a single supply rail. This configuration allows the circuit to achieve the necessary high pass filter characteristics and biasing functionality while using small integrated capacitor values, effectively mediating between the space constraints and the filter performance requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables a microphone circuit that meets the size requirements of portable devices by integrating the biasing circuit, ensuring that all frequency components above 20 Hz are not attenuated, while using conventional semiconductor manufacturing capabilities.

Implementation Method 1

The first capacitor is coupled between the first node and the second node

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

filters the first signal to generate a second signal at the second node

Methodology Applied
Scientific EffectHigh pass filter: Filter (electronic)

Data Source

PatentUS20090285412A1Integrated circuit biasing a microphone
Publication Date: 2009.11.19 FORTEMEDIA INC
  • US20090285412A1 patent drawing
  • US20090285412A1 patent drawing
  • US20090285412A1 patent drawing

AI summary

The invention provides an integrated circuit. The integrated circuit receives a first signal from a microphone via a first node. In one embodiment, the integrated circuit comprises a biasing circuit and a buffering circuit. The biasing circuit is coupled between the first node and a second node, drives the microphone with a first voltage source, and filters the first signal to generate a second signal at the second node. In one embodiment, the biasing circuit comprises a first resistor, a first capacitor, and a load element. The first resistor is coupled between the first voltage source and the first node. The first capacitor is coupled between the first node and the second node. The load element is coupled between the second node and a second voltage source. The buffering circuit is coupled between the second node and a third node and buffers the second signal to generate a third signal at the third node.