Oversampled Microphone Fractional Delay for Distortion-Free Beamforming

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Solution Overview

Problem

Existing digital microphone systems face challenges in interfacing analog signals with digital electronics, particularly in introducing a fractional time delay in the oversampled domain without disturbing the circuitry or impacting the Application Processor.

Innovation Solution

A programmable fractional time delay is introduced in the oversampled domain using a Fractional Delay Block, which receives the oversampled output from the PDM modulator and applies a time delay that is a fraction of a baseband clock period, programmable from 0 to 512 delay elements, using control logic and bidirectional I/O to manage the clock and L/R pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a fractional time delay is introduced using traditional FIR filters, then time delay is achieved, but distortion is incurred

Engineering Contradiction:
Improvetime delayVSAvoidsignal distortion
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent changes the fundamental parameter of time delay implementation from filter-based (FIR) to domain-based (oversampled). By operating in the oversampled domain where sampling frequency is much higher than baseband frequency, the system achieves fractional time delay as integer delays at the higher sampling rate, eliminating the distortion inherent in traditional FIR filter approaches.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If fractional time delay is implemented in the oversampled domain, then flexibility and precision are improved, but device complexity increases

Engineering Contradiction:
Improvetime delay programmabilityVSAvoidcircuitry complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary oversampled domain as a buffer between the analog input and baseband processing. This intermediary domain with higher sampling frequency enables precise fractional time delays to be implemented as simple integer delays, providing flexibility without requiring complex filter circuits in the baseband domain.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The time delay function is segmented into the oversampled domain where it can be implemented as simple buffer delays. The complex signal processing is separated from the time delay function, allowing each to be optimized independently - the oversampled domain handles timing precision while baseband handling achieves signal processing.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If existing system bus and Application Processor are used without modification, then ease of operation is maintained, but adaptability to fractional time delay is limited

Engineering Contradiction:
Improvesystem compatibilityVSAvoidfractional time delay capability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent adds another dimension - the oversampled domain - to the existing system architecture. Instead of modifying the baseband domain where the Application Processor operates, the invention introduces time delay control in the oversampled domain, allowing fractional delays while maintaining compatibility with existing baseband processing infrastructure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11646725B2Fractional time delay structures in digitally oversampled microphone systems, circuits, and methods
Publication Date: 2023.05.09 SOLOS TECH LTD
  • US11646725B2 patent drawing
  • US11646725B2 patent drawing
  • US11646725B2 patent drawing

AI summary

An apparatus to time delay a digital, signal output from an oversampled sensor includes a first time delay element and a second time delay element. The first time delay element has a first input and a first output. The first time delay element is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. An output of the oversampled sensor is connected to the first input of the first time delay element. The second time delay element has a second input and a second output and is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. The first output of the first time delay element is connected to the second input of the second time delay element. A multiplexer has a control input and a multiplexer output. The first output of the first time delay element is connected to a first multiplexer input. The second output of the second time delay element is connected to a second multiplexer input. In operation, time delay information is used to provide a signal to the control input to select a particular multiplexer input for output on the multiplexer output. The output of the oversampled sensor is time delayed by an amount provided by the particular multiplexer input.