Microprocessor Address Translation for ROM Patching
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Solution Overview
Problem
Existing program patching methods for microprocessor systems are inflexible, resource-intensive, and not applicable to all systems, particularly those with pipelined CPUs, as they require significant system load and cannot modify microprocessor addresses effectively.
Innovation Solution
A microprocessor system with a trap controller that uses a trap table, region table, and patch table to translate addresses from a first address bus to a second address bus, allowing for flexible program patching and code replacement or insertion without modifying the program counter or increasing system load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If one bit for each potential ROM address is used to indicate a program branch, then program patching capability is provided, but system load is heavily increased
Solution Approach 1:
The patent divides the address translation function into multiple specialized tables: trap table, region table, and patch table. Each table handles a specific aspect of address translation, breaking down the monolithic approach into manageable segments that reduce overall system complexity and resource requirements.
Solution Approach 2:
The patent introduces an address translation mechanism that acts as an intermediary between the microprocessor and the ROM. Instead of directly modifying program counters or using interrupt-based methods, the system uses address translation tables to redirect accesses to patched code, providing a more efficient mediation layer.
2Ease of operation
If program counter is modified for a branch, then program branching is achieved, but flexibility is reduced as it can only branch for one source/target pair
Solution Approach 1:
The patent implements dynamic address translation through the use of trap and region tables that can be configured at runtime. The system can adaptively translate addresses based on the current execution context, allowing multiple source/target pairs to be handled flexibly without modifying the program counter structure.
Solution Approach 2:
The system changes the parameters of address translation by using trap numbers and region definitions instead of fixed program counter modifications. This allows the same mechanism to handle multiple different branching scenarios by changing the translation parameters rather than the fundamental branching approach.
3Ease of repair
If microprocessor addresses are changed by hardware interrupt, then program patching is achieved, but applicability to pipelined CPU systems is lost
Solution Approach 1:
The patent uses an address translation intermediary that operates transparently to the microprocessor pipeline. Instead of relying on hardware interrupts that may conflict with pipelined execution, the system intercepts and translates addresses at the memory access level, making it compatible with various CPU architectures including pipelined designs.
Solution Approach 2:
The address translation mechanism is designed to be universally applicable across different microprocessor architectures. The trap controller and translation tables provide a architecture-independent method for program patching that can be implemented in various systems regardless of their specific CPU design or pipelining characteristics.
Data Source
AI summary
A microprocessor system contains a read-only memory (ROM) for storing programs or firmware. Retrieval and execution of program code is controlled by a microprocessor address bus. Erroneous data in the ROM can be corrected by address comparison and translation. Trap, region, and patch tables are provided to store addresses, regions, and translated addresses. An address issued by the microprocessor is stored in the trap and region tables can be translated for selecting another programmable device, such as a SRAM or DRAM, other than the original ROM. Thus, erroneous code in the ROM can be corrected, inserted, or replaced.