Microprocessor Software Routine Execution via Arithmetic Address Generation
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Solution Overview
Problem
Existing solutions for selectively executing software routines in microprocessors are vulnerable to security risks, particularly due to the use of conditional jump operations that can be exploited by attackers.
Innovation Solution
The implementation of combinational and arithmetic operations to generate result bit sequences that determine the execution of either a first or second software routine, without using explicit conditional jump operations, thereby enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conditional jump operations are used to selectively execute software routines, then the ease of operation is improved, but the reliability deteriorates due to security vulnerabilities
Solution Approach 1:
The patent extracts and removes the conditional jump operation from the execution flow. Instead of using conditional jumps to select between software routines, the invention uses a deterministic address calculation mechanism that computes the target address directly through arithmetic operations on result bit sequences, eliminating the vulnerable conditional branch instruction entirely.
Solution Approach 2:
The patent replaces the control flow mechanism (conditional jump) with a data flow mechanism (arithmetic calculation of memory address). The selection of which software routine to execute is determined by calculating an address based on result bit sequences rather than by a conditional branch instruction, substituting a mechanical control flow operation with a data processing operation that is inherently more secure.
2Reliability
If combinational and arithmetic operations are used to generate result bit sequences and determine execution addresses, then the reliability is improved by eliminating security vulnerabilities, but the device complexity increases
Solution Approach 1:
The patent employs a universal address calculation mechanism that can determine the execution address of any software routine through a single set of combinational and arithmetic operations. The same computational infrastructure (logic gates, adders, multiplexers) serves both the comparison function and the address generation function, rather than requiring separate dedicated circuits for each purpose.
Solution Approach 2:
The patent merges the comparison operation and the address selection operation into a single integrated process. The result bit sequences generated by comparing obtained data with expected values are directly fed into the address calculation logic, combining what could be separate functional blocks into a unified circuit that performs both comparison and conditional address generation in one operational flow.
3Measurement precision
If multiple result bit sequences are generated through combinational operations, then the measurement precision is improved for security verification, but the loss of time increases due to additional operations
Solution Approach 1:
The patent maintains continuous data flow through the computational pipeline. The result bit sequences are generated and immediately used in the address calculation without intermediate storage or sequential processing delays. The combinational logic operations occur in parallel, and the output of one stage directly feeds the next stage in an uninterrupted sequence, maximizing the utilization of each operational cycle.
Solution Approach 2:
The patent performs preliminary generation of result bit sequences through combinational operations on the obtained data and expected values before the address calculation begins. By pre-computing these result sequences and making them available in advance, the subsequent address determination can proceed without waiting for sequential comparison operations, reducing overall execution time.
Data Source
AI summary
First combinational, arithmetic, or combinational and arithmetic, operations are applied to data and an expected value, generating result bit sequences. When the value of the data corresponds to the expected value, the result bit sequences are different from each other and correspond to expected values of the result bit sequences. Second operations are applied a first memory address, a second memory address, and the result bit sequences, generating a memory address. When values of the generated result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address. When values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address. A software routine starting at the generated memory address is executed.