Microprocessor Data Memory Expansion via Bank Select
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Solution Overview
Problem
Low-cost 8-bit microprocessors and microcontrollers, such as the PIC16 family, have limited data memory capacity due to restricted addressing capabilities, which restricts the number of general-purpose registers and memory locations, necessitating an expansion of data memory while maintaining instruction set compatibility.
Innovation Solution
Implementing a bank select accessing scheme with a 6-bit bank select register and a dedicated instruction for memory bank selection, allowing for up to 64 memory banks and enabling indirect addressing to expand the data memory capacity, while ensuring compatibility with existing architectures by repurposing test instructions and modifying the opcode structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a bank select mechanism is used to expand data memory, then the data memory capacity is improved, but the instruction set complexity increases
Solution Approach 1:
The data memory is segmented into multiple banks (e.g., 4 banks of 128 bytes each to achieve 512 bytes total). Each bank can be independently selected using a bank select register, allowing the limited instruction word address space to access different segments of the total memory space through sequential bank switching.
Solution Approach 2:
A bank select register acts as an intermediary between the instruction set and the memory banks. This register holds the current bank selection value and is updated by specific instructions, mediating the access to different memory banks without requiring changes to the fundamental instruction word structure.
2Device complexity
If the bank select register is part of a status register, then the device complexity is reduced, but the data memory capacity is limited
Solution Approach 1:
The bank select register is merged with the status register in low-cost implementations. This combines multiple functions (status flags and bank selection) into a single register structure, reducing the overall device complexity while still enabling access to multiple memory banks through the existing status register interface.
Solution Approach 2:
The status register is given multi-functionality by incorporating the bank select capability. This allows the same register to serve both as a status indicator and as a bank selection mechanism, eliminating the need for a separate dedicated bank select register and thereby reducing device complexity.
3Device complexity
If certain memory locations are used to memory map special function registers, then the device complexity is reduced, but the general purpose register availability is reduced
Solution Approach 1:
The memory banks are segmented into different regions: special function registers (SFRs) occupy fixed addresses in each bank, while the remaining addresses are allocated to general purpose registers (GPRs). This segmentation allows SFRs to be memory-mapped for easy access while maximizing the available space for user-programmable GPRs in each bank.
Solution Approach 2:
Different memory locations within each bank have different qualities or functions. The lower address range is dedicated to SFRs with specific control functions, while the upper address range is allocated to GPRs for general computation. This local differentiation optimizes both device control capability and user programming flexibility within the same memory bank structure.
Data Source
Figure 1
Figure 1A
Figure 2~3A
AI summary
A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.