Microprocessor Binary Translation for Safety Redundancy
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Solution Overview
Problem
Modern microprocessors, especially those in automotive systems, face challenges in executing program code from different instruction-set architectures and ensuring safety-relevant functions with redundancy, as they are often not explicitly designed for automotive use, leading to high development costs and difficulties in adapting hardware for new functions.
Innovation Solution
A method utilizing dynamic binary translation software that converts source instructions from one architecture to another, replicates and renames target instructions for redundant execution, and includes error detection and correction mechanisms, allowing for the execution of safety-relevant functions without modifying hardware, and enabling updates through software modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If program code is translated from a first instruction-set architecture to a second instruction-set architecture using conversion software, then compatibility with different microprocessor architectures is improved, but device complexity increases due to the additional translation layer
Solution Approach 1:
The patent employs conversion software as an intermediary layer between program code and the microprocessor execution unit. This mediator translates source instructions from a first instruction-set architecture into target instructions for a second instruction-set architecture, enabling cross-architecture compatibility without modifying the underlying hardware. The conversion software acts as a buffer that resolves the incompatibility between different ISA formats.
2Reliability
If target instructions are replicated with renamed memory areas for redundant execution, then reliability for safety-critical functions is improved, but processing time increases due to duplicate execution
Solution Approach 1:
The conversion software performs preliminary replication of target instructions before execution, creating multiple copies with renamed memory area references. This advance preparation allows the microprocessor to execute redundant instructions simultaneously or in rapid succession, ensuring that safety-critical functions have verified results without significant time penalty. The replication is done in advance of the actual execution phase.
3Adaptability or versatility
If hardware is modified to support new functions or automotive-specific requirements, then functionality for safety-relevant applications is improved, but manufacturing cost and development complexity increase
Solution Approach 1:
The patent implements a dynamic software-based adaptation mechanism that allows the microprocessor to adjust its behavior and supported functions through conversion software updates rather than hardware modifications. The conversion software can be dynamically loaded, updated, or configured to support new instruction-set architectures or safety protocols, providing flexibility without requiring physical hardware changes. This dynamic approach enables the same hardware platform to serve multiple automotive applications.
Data Source
AI summary
A method is described for operating a microprocessor, in which a conversion software executed in the microprocessor carries out a binary translation, in the course of which a source instruction that is encoded according to a first instruction-set architecture is translated into a target instruction in a binary manner, which is encoded according to a second instruction-set architecture, and the target instruction translated by the translation software into the second instruction-set architecture being replicated, and in this replicated target instruction a memory area which is to be accessed in the course of the execution of the target instruction is replaced by a second memory area, and the target instruction and the copied target instruction is executed by the microprocessor. With the aid of the method, a temporal redundancy is achieved by a (temporally) parallel execution of the target instruction on a processor core and a local or regional redundancy by a parallel execution of the target instruction on different processor cores.