Microprocessor Breakpoint Check for Cache Line-Crossing Loads
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Solution Overview
Problem
Microprocessors face complexity in performing breakpoint checks for cache-line-crossing load/store operations due to the need to maintain virtual addresses across multiple cache line accesses, leading to increased storage requirements and pipeline passes, which are undesirable in terms of die real estate and power consumption.
Innovation Solution
A microprocessor design that performs a full breakpoint check in no more than two passes through the load/store unit pipeline by using a breakpoint register and a queue with indicator storage to manage address comparisons, allowing the load/store unit to access cache memory efficiently across cache line boundaries without additional address fields or pipeline passes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a second address field is added to each load queue entry to preserve virtual addresses for breakpoint checking, then breakpoint checking accuracy is improved, but die real estate and power consumption increase significantly
Solution Approach 1:
The patent extracts only the necessary portion of the address information (page address portion) that is needed for breakpoint checking, rather than storing the complete virtual address. This selective extraction allows breakpoint checking to proceed without requiring additional full address storage, thereby resolving the contradiction between checking accuracy and die real estate requirements.
Solution Approach 2:
The patent creates a copy of only the relevant page address portion in a separate indicator field, rather than duplicating the entire address. This partial copying enables breakpoint verification while minimizing additional storage requirements, thus balancing accuracy needs with area constraints.
2Measurement precision
If additional passes through the load pipeline are performed to check breakpoints for each piece, then breakpoint checking completeness is improved, but processing speed decreases
Solution Approach 1:
The patent performs preliminary breakpoint checking during the first pass through the pipeline by comparing the page address portion against breakpoint ranges. This advance checking ensures breakpoint compliance is verified before the data is actually accessed, maintaining completeness while avoiding the need for additional pipeline passes and preserving processing speed.
Solution Approach 2:
The patent performs a simplified breakpoint check using only the necessary page address portion rather than a complete address verification. This partial action is sufficient for breakpoint detection purposes and allows the check to be completed within the existing pipeline timeline without requiring additional passes.
3Quantity of substance
If the virtual address is clobbered during the first piece processing, then storage requirements are reduced, but the ability to perform breakpoint checking on the second piece is lost
Solution Approach 1:
The patent extracts and preserves only the essential page address portion in a separate indicator field before the virtual address is clobbered during normal pipeline processing. This selective extraction maintains the minimal information needed for breakpoint checking on the second piece while allowing the main address field to be overwritten, thus resolving the contradiction between storage efficiency and checking capability.
Data Source
AI summary
A microprocessor breakpoint-checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.