Microprocessor Cache Querying for Data Acquisition Efficiency
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Solution Overview
Problem
The performance gap between microprocessors and memory access times is significant due to the slow access speed of main memory, which is mitigated by using SRAMs but at the cost of low storage density and high cost, and the strict separation of instruction and data caches in Harvard Architecture leads to a low cache hit ratio.
Innovation Solution
A data acquisition method and microprocessor design that physically separates instruction and data caches while allowing them to query each other, enabling target information to be returned from the non-matching cache if not found in the requested type's cache, effectively improving data acquisition efficiency and cache capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instruction cache and data cache are strictly separated in Harvard Architecture, then data acquisition efficiency is improved, but cache hit ratio decreases
Solution Approach 1:
The patent applies universality by enabling both instruction cache and data cache to serve dual purposes. The instruction cache can store both instructions and data, while the data cache can store both data and instructions. When a cache miss occurs in the traditionally designated cache, the system can search in the other cache, effectively making each cache unit universal and increasing the overall cache hit ratio while maintaining data acquisition efficiency
2Speed
If SRAM is used to mitigate slow main memory access, then access speed is improved, but storage density decreases and cost increases
Solution Approach 1:
The patent merges the functionality of instruction cache and data cache into a unified cache system where both cache units can store and retrieve both instructions and data. This combination allows the system to maximize the utilization of SRAM resources, achieving faster access speeds while improving overall storage efficiency by eliminating the need for completely separate instruction and data storage paths
Data Source
AI summary
The present application discloses a data acquisition method, a microprocessor and an apparatus with storage function. The method may include: a request information for obtaining a target information may be received. The request type of the request information may be an instruction request or a data request. The instruction cache and the data cache may be queried respectively, to determine whether the target information matching with the requested information exits in the instruction cache and the data cache. If the target information exists in another cache that does not match with the request type of the request information, then the target information may be returned from the cache that does not match with the request type of the request information. The present application may physically separate the instruction cache and the data cache, thereby improving the data acquisition efficiency.