Multi-core Microprocessor Cache Restoral via Fuse Array Compression
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Solution Overview
Problem
Current semiconductor fuse arrays on multi-core microprocessors require significant real estate and power to store and provide configuration/repair data, and face challenges in initializing and configuring devices quickly following power gating events due to increased complexity and transistor size limitations.
Innovation Solution
A semiconductor fuse array programmed with compressed configuration data for multiple cores, coupled with sub-stores that decompress and store configuration data sets for cache memories, allowing for efficient retrieval and initialization upon power-up/reset, reducing the need for extensive real estate and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional semiconductor fuse arrays are used to store configuration and repair data for multiple cores, then the data can be stored on-die, but the real estate required and power consumption increase significantly
Solution Approach 1:
The system divides configuration data into two segments: compressed data stored in the fuse array and decompressed data stored in external memory structures. This segmentation allows the fuse array to store only compacted representation while the full configuration data resides externally, reducing on-die area while maintaining full data capacity.
Solution Approach 2:
The system transitions from storing all configuration data in a single on-die fuse array to a multi-dimensional storage architecture where compressed data resides in the fuse array and decompressed data is stored in external memory structures accessible by multiple cores. This dimensional change in data storage architecture reduces the area footprint while preserving data availability.
2Quantity of substance
If traditional fuse arrays are used for multi-core devices, then configuration data can be provided, but power consumption increases and initialization following power gating events is slow
Solution Approach 1:
The system segments the configuration data storage function between the fuse array (storing compressed data) and external memory structures (storing decompressed data). This segmentation allows power-efficient access where only the necessary decompression and data retrieval operations are performed, reducing overall power consumption compared to maintaining large on-die fuse arrays.
Solution Approach 2:
Configuration data is decompressed and pre-loaded into external memory structures during manufacturing or initial setup. This preliminary action ensures that when the device operates or wakes from power gating, the fully decompressed configuration data is already available in external memory, eliminating the need for time-consuming decompression operations during runtime or wake-up sequences.
3Area of stationary object
If compressed configuration data is stored in the fuse array and decompressed in external memory, then real estate and power are reduced, but additional decompression logic and memory structures are required
Solution Approach 1:
The system introduces an intermediary decompression logic component that bridges the fuse array and external memory structures. This intermediary performs the compression/decompression function and coordinates data transfer between the compacted fuse storage and the expanded external memory, managing the complexity of the multi-layer storage architecture through a dedicated control interface.
4Reliability
If all cores access the fuse array for configuration data, then data consistency is maintained, but initialization time following power gating events increases
Solution Approach 1:
The system performs preliminary decompression of configuration data during manufacturing or initial setup, storing the decompressed data in external memory structures. This preliminary action ensures that when cores need configuration data, especially after power gating events, they can directly retrieve pre-decompressed data from external memory without waiting for decompression operations, significantly reducing initialization time while maintaining data consistency through controlled access protocols.
Data Source
AI summary
An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches.