Microprocessor Compressed Microcode Memory Segmentation
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Solution Overview
Problem
Modern microprocessors face challenges in managing the increasing complexity and memory requirements of microcode, particularly in multi-core processors, where the proliferation of cores leads to significant memory storage needs for microcode, resulting in real estate consumption and latency issues.
Innovation Solution
A microprocessor design that includes multiple memories for storing both compressed and uncompressed microcode instructions, with a decompression unit that selectively decompresses compressed instructions before execution, allowing for reduced memory width and size while maintaining efficient instruction execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If microcode memories are made larger to store more instructions, then the instruction set complexity increases, but the die area consumption increases significantly
Solution Approach 1:
The microcode memory is divided into multiple separate memory modules, each storing a subset of microcode instructions. This segmentation allows the system to access only the required microcode subset for a given instruction, reducing the effective memory size needed while maintaining full instruction set support capability.
Solution Approach 2:
The patent introduces a new dimension of memory organization by using multiple memory modules with different capacities and characteristics. Instead of a single large memory, the system uses a multi-dimensional memory structure where each module can be independently sized and optimized for specific instruction types.
2Quantity of substance
If microcode memories are made wider to accommodate more instructions, then more instructions can be stored, but the memory width and storage needs increase
Solution Approach 1:
The microcode instruction set is segmented across multiple memory modules, each with narrower width but collectively providing the full instruction capacity. This allows the system to store a large number of instructions without requiring any single memory module to have excessive width.
Solution Approach 2:
Each memory module is optimized with local quality characteristics, having different widths and capacities suited to specific instruction categories. This allows each module to be efficiently sized for its specific purpose rather than all modules having uniform maximum width.
3Area of stationary object
If compressed microcode is used to reduce memory size, then die area is minimized, but latency may increase due to decompression requirements
Solution Approach 1:
The microcode instructions are pre-compressed during the memory design phase, and the decompression is performed as part of the normal fetch-decode-execute cycle. This preliminary compression allows the system to maintain smaller memory sizes while the decompression overhead is amortized across the standard instruction execution timeline.
Solution Approach 2:
A decompression unit acts as an intermediary between the compressed microcode memory and the instruction execution pipeline. This intermediary component handles the decompression transparently, allowing the rest of the system to operate without awareness of the compression scheme while maintaining efficient throughput.
Data Source
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AI summary
A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.