Microprocessor Cryptography Unit Atomic Instruction
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Solution Overview
Problem
Current computer systems face inefficiencies in performing cryptographic operations due to the need for multiple instances of encryption/decryption applications, slow software-based implementations, and increased system processing delays, particularly in multi-tasking environments and networked systems.
Innovation Solution
A microprocessor apparatus with a dedicated cryptography unit that performs cryptographic operations via a single atomic instruction, reducing the need for operating system intervention and supporting multiple algorithms, modes, and key sizes, while being compatible with legacy systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based encryption/decryption applications are used, then cryptographic operations can be performed, but processing speed is slow and system delays increase
Solution Approach 1:
The patent extracts the cryptographic operation functionality from the general software application layer and implements it as a dedicated hardware unit within the microprocessor. This cryptography unit operates independently of the main software execution path, allowing cryptographic operations to be performed at hardware speed without blocking application tasks, thereby resolving the contradiction between cryptographic operation speed and system processing efficiency
Solution Approach 2:
The patent introduces an intermediary hardware layer between the software application and the cryptographic processing. The dedicated cryptography unit acts as a mediator that receives cryptographic requests from software, executes them at hardware speed, and returns results, thus decoupling the slow software processing from the fast cryptographic operations and improving overall system productivity
2Adaptability or versatility
If multiple instances of encryption/decryption applications are run, then various cryptographic tasks can be handled, but system resources are consumed and tasks must be suspended
Solution Approach 1:
The patent implements a universal cryptography unit within the microprocessor that can handle multiple cryptographic algorithms and modes of operation through a single integrated hardware structure. This multi-functional unit eliminates the need for separate dedicated hardware instances for each cryptographic task, reducing system resource consumption while maintaining the ability to handle diverse cryptographic operations
Solution Approach 2:
The patent merges multiple cryptographic processing functions into a single integrated hardware unit. By combining encryption, decryption, and other cryptographic operations in one dedicated unit, the system can handle multiple cryptographic tasks concurrently without requiring separate application instances, thereby reducing resource consumption and eliminating task suspension needs
3Device complexity
If atomic instructions with single opcode are used, then device complexity is reduced, but implementing multiple algorithms and modes becomes difficult
Solution Approach 1:
The patent employs dynamic control within the single opcode instruction to specify different cryptographic algorithms and modes of operation. The instruction set uses variable-length parameter fields and control words that can be dynamically configured at runtime, allowing the same atomic instruction structure to adapt to different algorithm requirements without increasing instruction set complexity
Solution Approach 2:
The patent implements versatility through parameter changes within the instruction structure. By using variable parameters such as key size, algorithm type, and mode of operation that can be specified within the atomic instruction, the system can support multiple cryptographic algorithms and modes while maintaining a simple unified instruction format, thus resolving the contradiction between device complexity and adaptability
Data Source
AI summary
A microprocessor apparatus is provided, for performing a cryptographic operation. The microprocessor apparatus includes an x86-compatible microprocessor that has fetch logic, a cryptography unit, and an integer unit. The fetch logic is configured to fetch an application program from memory for execution by the x86-compatible microprocessor. The application program includes an atomic instruction that directs the x86-compatible microprocessor to perform the cryptographic operation. The atomic instruction has and opcode field and a repeat prefix field. The opcode field prescribes that the device accomplish the cryptographic operation as further specified within a control word stored in a memory. The repeat prefix field is coupled to the opcode field. The repeat prefix field indicates that the cryptographic operation prescribed by the atomic instruction is to be accomplished on a plurality of blocks of input data.