Microprocessor Display Interface Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microprocessor systems with integrated graphics engines face high costs and energy inefficiencies due to the combination of processor cores and graphics engines on a single chip, which is unsustainable for mid-range or high-end systems, and require inefficient bandwidth usage for display refresh data transfer in Unified Memory Architecture (UMA) systems.
Innovation Solution
A microprocessor system design where the processor core and graphics engine are separate entities, with the graphics engine external to the south bridge, allowing for a shared memory interface and a dedicated display interface to manage graphical information, enabling the graphics engine to be powered off during idle periods and offloading simple graphics processing to the processor core, thus optimizing power usage and reducing unnecessary interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the graphics engine is integrated into the processor core on the same chip, then the system achieves high performance and low latency for graphical operations, but the manufacturing cost and chip complexity become unacceptably high
Solution Approach 1:
The patent divides the graphics system into separate components: the processor core and the graphics engine are placed on different chips (processor and south bridge respectively), connected via bus interfaces. This segmentation reduces individual chip complexity while maintaining system performance through efficient inter-chip communication.
Solution Approach 2:
The patent introduces a dedicated display interface on the processor that acts as an intermediary between the graphics engine and the display device. This interface receives graphical data from the south bridge and manages display operations independently, reducing the communication burden on the processor core.
2Device complexity
If the graphics engine is integrated into the south bridge, then the system reduces chip complexity and manufacturing cost, but the bandwidth for display refresh data transfer is reduced due to the front-side bus
Solution Approach 1:
The patent segments the display interface functionality from the graphics engine, placing the display interface on the processor while keeping the graphics engine on the south bridge. This allows the display interface to access display refresh data directly from memory without requiring transfer through the front-side bus, preserving bandwidth.
Solution Approach 2:
The display interface on the processor serves as an intermediary that directly accesses memory for display refresh data, bypassing the need for data to traverse the front-side bus. This eliminates the bandwidth bottleneck that would otherwise exist in integrated south bridge configurations.
3Device complexity
If the display interface is integrated into the graphics engine on the same chip, then the system reduces the number of separate interfaces, but energy consumption increases due to continuous data transfer requirements
Solution Approach 1:
The patent separates the display interface from the graphics engine, placing the display interface on the processor and the graphics engine on the south bridge. This segmentation allows the display interface to operate independently with its own dedicated memory access path, enabling power-down during idle periods without affecting graphics processing capabilities.
Solution Approach 2:
The patent enables periodic power-down of the graphics engine during idle display refresh periods. The display interface continues to function independently by accessing memory directly, allowing the graphics engine to be powered off during periods when no graphical processing is needed, thereby reducing energy consumption.
Data Source
AI summary
A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.