Microprocessor Fault Detection via On-Line Testing and Checkpointing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As silicon technologies advance into the nanometer regime, concerns about transistor reliability increase due to device scaling, leading to issues like gate oxide wear-out, transistor infant mortality, and manufacturing defects that escape testing, which can compromise component yield and lifetime.
Innovation Solution
A mechanism is provided to protect microprocessor pipelines and on-chip memory systems from silicon defects using area-frugal on-line testing techniques combined with system-level checkpointing, enabling speculative computational epochs for verifying hardware integrity and rolling back to a known-good state in case of defects, allowing continued operation in a degraded performance mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is pursued to improve transistor density and performance, then productivity increases, but reliability deteriorates due to gate oxide wear-out, transistor infant mortality, and manufacturing defects
Solution Approach 1:
The patent implements preliminary action by performing on-line testing and microarchitectural checkpointing before defects can cause system failure. The system continuously monitors hardware integrity during operation and rolls back to checkpointed states if defects are detected, preventing reliability issues from compromising the scaled transistors' productivity benefits
Solution Approach 2:
The patent introduces an intermediary testing mechanism that mediates between the scaled transistors and system operation. The on-line testing infrastructure acts as a mediator to detect defects early, while checkpointing provides intermediate recovery points, allowing the system to maintain productivity from scaled devices without sacrificing reliability
2Reliability
If aggressive burn-in testing is applied to eliminate infant mortality failures, then reliability improves, but device yield deteriorates due to thermal run-away effects destroying robust devices
Solution Approach 1:
The patent replaces expensive, destructive burn-in testing with a cheaper, non-destructive on-line testing approach. Instead of subjecting devices to extreme stress that can destroy robust transistors, the system uses continuous monitoring during normal operation to detect defects, maintaining high yield while achieving reliability goals
Solution Approach 2:
The system performs self-service reliability validation through on-line testing and self-diagnosis. The microprocessor automatically monitors its own hardware integrity during operation, eliminating the need for external aggressive burn-in testing that reduces yield, while still identifying and isolating defective components
3Reliability
If manufacturing testing time is increased to detect defects, then reliability improves, but productivity deteriorates due to extended test duration affecting manufacturing throughput
Solution Approach 1:
The patent implements periodic on-line testing during microprocessor operation rather than requiring extended continuous testing during manufacturing. The system performs testing at periodic intervals during normal operation, allowing manufacturing throughput to maintain high productivity while still achieving comprehensive defect detection for improved reliability
Solution Approach 2:
The system maintains continuity of useful action by performing testing during normal microprocessor operation rather than requiring separate manufacturing test phases. The on-line testing occurs continuously or periodically while the processor is operational, eliminating the trade-off between testing duration and manufacturing throughput
4Reliability
If on-line testing and checkpointing are implemented to detect silicon defects, then reliability improves, but area cost increases due to additional testing infrastructure
Solution Approach 1:
The patent applies partial action by implementing on-line testing and checkpointing selectively in critical microarchitectural components rather than throughout the entire chip. This targeted approach achieves sufficient reliability improvement while minimizing the area overhead associated with testing infrastructure
Solution Approach 2:
The system segments the microprocessor into testable modules with individual checkpointing capability. By dividing the architecture into separable units that can be independently tested and rolled back, the patent reduces the overall area cost compared to a monolithic testing approach, as each segment requires only local testing resources
Data Source
AI summary
A microprocessor has a silicon area comprising a plurality of transistors implemented on the silicon area and a fault detection circuit occupying less than 20% of the silicon area and configured to detect faults at runtime in at least 80% of the plurality of transistors.