Microprocessor Fusing Load-ALU-Store and JCC Instructions
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Solution Overview
Problem
Conventional microprocessors require additional resources and clock cycles to translate load-arithmetic-store and conditional jump macroinstructions into micro-operations, limiting instruction throughput and increasing pipeline complexity.
Innovation Solution
A microprocessor design that fuses load-arithmetic-store and conditional jump macroinstructions into three micro-operations, allowing simultaneous translation and execution, reducing resource consumption and increasing instruction per clock cycle rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional microprocessors translate load-arithmetic-store and conditional jump macroinstructions separately into micro-operations, then each instruction can be executed independently, but the instruction throughput is limited and pipeline complexity increases
Solution Approach 1:
The patent merges the translation of load-arithmetic-store macroinstructions and conditional jump macroinstructions into a single simultaneous translation operation. The instruction translator is configured to translate both types of macroinstructions into their respective micro-operations in one clock cycle, reducing the number of translation operations and increasing instruction throughput while simplifying the pipeline structure.
2Reliability
If additional resources are allocated for translating separate macroinstructions, then translation accuracy is maintained, but resource consumption increases
Solution Approach 1:
The instruction translator is designed with multi-functionality to handle both load-arithmetic-store macroinstructions and conditional jump macroinstructions using the same translation resources. By implementing a unified translation mechanism that can process different instruction types simultaneously, the patent maintains translation accuracy while reducing the total resource consumption compared to separate dedicated translation paths.
Data Source
AI summary
A microprocessor receives first and second program-adjacent macroinstructions of the microprocessor instruction set architecture. The first macroinstruction loads an operand from a location in memory, performs an arithmetic/logic operation using the loaded operand to generate a result, and stores the result back to the memory location. The second macroinstruction jumps to a target address if condition codes satisfy a specified condition and otherwise executes the next sequential instruction. An instruction translator simultaneously translates the first and second program-adjacent macroinstructions into first, second, and third micro-operations for execution by execution units. The first micro-operation calculates the memory location address and loads the operand therefrom. The second micro-operation performs the arithmetic/logic operation using the loaded operand to generate the result, updates the condition codes based on the result, and jumps to the target address if the updated condition codes satisfy the condition. The third micro-operation stores the result to the memory location.