Microprocessor Hardware Translation for x86 and ARM ISA Compatibility
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Solution Overview
Problem
Computing device manufacturers and users face challenges in supporting multiple instruction set architectures, leading to wasted investments due to the need for separate systems for x86 and ARM architectures, as demand shifts between these architectures, and existing solutions like software translators do not provide sufficient performance for many users.
Innovation Solution
A microprocessor design capable of running both x86 and ARM instruction set architectures by using a hardware instruction translator to translate instructions into microinstructions, with a mode indicator to manage architectural state and support for resetting between architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate systems are used for x86 and ARM architectures, then each architecture can be optimized for its specific market segment, but manufacturing cost and device complexity increase due to maintaining multiple system configurations
Solution Approach 1:
The patent implements a universal processor design that can execute both x86 and ARM instruction sets through a common execution pipeline. The processor includes architecture-agnostic components such as a generic instruction decoder, unified register file, and shared execution units that can handle instructions from either architecture, eliminating the need for separate dedicated processors for each architecture while maintaining optimized performance for both.
Solution Approach 2:
The processor is divided into architecture-specific front-end components (separate decoders and state machines for x86 and ARM) and a shared back-end execution pipeline. This segmentation allows each architecture to have its own optimized instruction decoding and control logic while sharing the expensive execution resources, thereby reducing overall complexity compared to having completely separate systems.
2Adaptability or versatility
If software translators are used to enable cross-architecture execution, then architecture versatility is improved, but execution performance deteriorates due to translation overhead
Solution Approach 1:
The patent replaces the software-based translation mechanism with hardware-based direct execution. Instead of translating x86 or ARM instructions into an intermediate representation and then executing them (which incurs software overhead), the processor uses architecture-specific front-end decoders that directly generate control signals for the shared execution pipeline, eliminating translation overhead and achieving near-native performance for both architectures.
3Adaptability or versatility
If a single processor supports multiple instruction set architectures, then investment preservation is improved, but instruction set complexity increases making development more difficult
Solution Approach 1:
The processor architecture is segmented into independent front-end modules for x86 and ARM, each containing its own instruction decoder and architectural state machine. These front-ends are connected to a shared back-end execution pipeline through a unified interface. This segmentation isolates the complexity of each instruction set implementation, allowing developers to work on one architecture at a time while sharing the common execution infrastructure.
Solution Approach 2:
The shared execution pipeline implements universal, architecture-agnostic execution logic that can perform operations required by both x86 and ARM instruction sets. The pipeline includes general-purpose execution units, a unified register file with architecture-independent addressing, and a common control logic that handles both architectures' control flow mechanisms, thereby reducing the overall implementation complexity compared to having separate dedicated pipelines.
Data Source
AI summary
A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs, the microprocessor comprising:a mode indicator, that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program; and a plurality of hardware registers, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, wherein when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state; wherein when one of the x86 ISA machine language program instructions writes a value to one of the plurality of hardware registers and one of the instructions of the ARM ISA machine language program subsequently reads the one of the plurality of hardware registers, the ARM ISA instruction receives the same value written by the x86 ISA instruction.