Microprocessor Indirect Addressing Bank Access
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Solution Overview
Problem
Existing microcontrollers face limitations in memory access, particularly in switching between memory banks, which hampers performance and functionality.
Innovation Solution
An n-bit microprocessor architecture with memory-mapped special function registers, indirect memory address registers, and a bank access unit allows for seamless access across all memory banks, including virtual registers that enable indirect addressing for both data and program memory, enhancing memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a banking system with separate data memory banks is used, then memory organization is improved and data protection is enhanced, but access time increases due to bank switching requirements
Solution Approach 1:
The data memory is divided into multiple banks (Bank 0, Bank 1, Bank 2, Bank 3) that can be independently accessed. Each bank contains specific registers and memory locations, allowing parallel organization and reducing contention for shared resources. This segmentation enables the system to maintain structured memory organization while reducing access time through direct bank selection.
Solution Approach 2:
The bank selection is performed in advance through the Bank Select Register (BSR) before data access operations. By pre-configuring which bank is active, the system eliminates the need for dynamic bank switching during data operations, thereby reducing access time while maintaining the benefits of organized memory banks.
2Adaptability or versatility
If indirect addressing is implemented across all banks, then memory access flexibility is improved, but register complexity increases
Solution Approach 1:
The indirect addressing registers (INDF0-INDF3) are designed to work universally across all memory banks without requiring separate indirect addressing mechanisms for each bank. A single indirect addressing mode can access any bank by combining the indirect register with the currently selected bank, reducing overall system complexity while maintaining high flexibility.
Solution Approach 2:
The indirect addressing registers serve as intermediaries between the CPU and the actual data memory locations. Instead of directly addressing memory locations, the CPU uses indirect registers that hold the target addresses, simplifying the addressing logic while enabling flexible access to any memory bank through the bank selection mechanism.
3Ease of operation
If virtual registers are added for indirect access, then programming ease is improved, but hardware implementation complexity increases
Solution Approach 1:
Virtual registers are implemented as software abstractions that mirror the functionality of physical registers without requiring separate physical hardware for each virtual register. The virtual register operations are handled through the existing physical register file and bank selection logic, providing enhanced programming ease while avoiding proportional increases in hardware complexity.
Data Source
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AI summary
An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.