Microprocessor Instruction Issue via Scenario-Based Conflict Resolution

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Solution Overview

Problem

Superscalar processors face performance bottlenecks due to hardware resource conflicts among instructions competing for execution resources, leading to increased latency and complexity in ensuring compatibility for parallel execution.

Innovation Solution

A high-speed mechanism is introduced that identifies and selects a collection of compatible issue-ready instructions for parallel execution by defining scenarios with predefined groups of instructions, using parallel finding circuits to identify instructions and selection logic to prioritize based on predefined policies, ensuring compatibility and forward progress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If extra register file ports are added to eliminate dependency among functional units, then register file bandwidth is sufficient for each functional unit, but logic complexity and manufacturing cost increase

Engineering Contradiction:
Improveregister file bandwidthVSAvoidlogic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent pre-organizes instructions into scenario-based groups before issue, where each scenario represents a pre-validating set of compatible instructions. This preliminary organization eliminates the need for complex real-time compatibility checking and additional register file ports, as the grouping is done in advance based on resource conflict constraints.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The instruction queue is segmented into multiple scenario groups, each representing a different execution context or resource configuration. By dividing the instruction stream into these predefined scenarios, the system can select appropriate groups without requiring additional register file ports or complex compatibility checking logic.

Inventive Principle:
Principle #1Segmentation

2Reliability

If complex find-second logic is used to identify the second-oldest compatible instruction, then compatibility among picked instructions is guaranteed, but latency increases due to serial operation of add circuits

Engineering Contradiction:
Improvecompatibility guaranteeVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Compatibility relationships between instructions are pre-computed and stored in scenario definitions before execution. Instead of performing serial compatibility checks during instruction selection, the system uses pre-validated scenario groups where compatibility is already established, eliminating the need for complex find-second logic and reducing latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically selects from multiple predefined scenarios based on current instruction queue state and resource availability. This dynamic scenario selection allows the system to adapt to different execution contexts without performing complex real-time compatibility analysis, thereby reducing latency while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

3Productivity

If multiple instructions are issued in parallel to improve execution throughput, then execution parallelism is enhanced, but resource conflicts increase among instructions competing for execution resources

Engineering Contradiction:
Improveexecution parallelismVSAvoidresource conflicts
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

Instructions are pre-grouped into scenarios where each group represents a set of instructions that are guaranteed to be compatible for parallel execution. By selecting from these pre-validated scenarios, the system can issue multiple instructions in parallel without resource conflicts, as compatibility is ensured by the scenario definition rather than runtime checking.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The scenario selection mechanism acts as an intermediary between the instruction queue and functional units. It mediates resource allocation by selecting scenarios that are compatible with current resource availability, thereby enabling parallel execution while preventing resource conflicts through intelligent scenario-based dispatch.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11900120B2Issuing instructions based on resource conflict constraints in microprocessor
Publication Date: 2024.02.13 MARVELL ASIA PTE LTD
  • US11900120B2 patent drawing
  • US11900120B2 patent drawing
  • US11900120B2 patent drawing

AI summary

Systems and methods of selecting a collection of compatible issue-ready instructions for parallel execution by functional units in a superscalar processor in a single clock cycle. All possible instructions (opcodes) to be executed by the functional units are pre-arranged into several scenarios based on potential resource conflicts among the instructions. Each scenario includes multiple groups of predefined instructions. During operation, concurrently for all the groups, an issue-ready instruction is identified with reference to each group based on group-specific selection policies. Further, based on the identified instructions, predefined policies are applied to select one or more scenarios and select among the picks of the selected scenarios. As a result, the output instructions of the selected scenarios are issued for parallel execution by the functional units.