Microprocessor Instruction Translation for x86 ARM Compatibility
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Solution Overview
Problem
Computing device manufacturers and users face challenges in running both x86 and ARM architecture programs due to the dilemma of which architecture to invest in, as software availability and performance can shift, leading to wasted investments and resource inefficiencies.
Innovation Solution
A microprocessor capable of hardware translating both x86 and ARM ISA instructions into microinstructions, allowing for direct execution by a common execution pipeline, thereby enabling the running of both x86 and ARM machine language programs efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a microprocessor is designed to support both x86 and ARM architectures, then versatility is improved, but device complexity increases
Solution Approach 1:
The microprocessor is designed with a universal execution pipeline that can execute both x86 and ARM machine language instructions directly, eliminating the need for separate processing paths or software translators for each architecture. This multi-functional design allows a single processor to serve multiple architecture requirements.
Solution Approach 2:
The patent introduces a common execution pipeline as an intermediary component that receives instructions from both x86 and ARM instruction sets and translates/executes them into a unified microinstruction format. This mediator approach simplifies the overall system architecture by providing a single translation path rather than multiple separate translation mechanisms.
2Speed
If hardware translation is implemented, then execution speed is improved, but device complexity increases
Solution Approach 1:
The translation hardware is merged with the execution pipeline itself, rather than being implemented as a separate pre-processing stage. The execution pipeline is designed to directly interpret and execute both x86 and ARM instructions as microinstructions, combining the translation and execution functions into a single unified structure.
Solution Approach 2:
The execution pipeline is designed as a universal structure that can directly execute multiple instruction set architectures without requiring architecture-specific execution paths. This multi-functional pipeline handles both x86 and ARM instructions through a common execution mechanism, reducing overall system complexity.
3Productivity
If conditional load or store instructions are translated into a variable number of microinstructions, then execution efficiency is improved, but translation complexity increases
Solution Approach 1:
The translation mechanism dynamically adjusts the number of microinstructions generated from conditional load or store instructions based on the specific instruction type and conditions. Rather than using a fixed translation scheme, the system adapts the translation depth and complexity to match the actual execution requirements, improving throughput while managing translation complexity.
Solution Approach 2:
The patent changes the parameter of instruction translation from a fixed one-to-one or one-to-many mapping to a variable mapping where the number of microinstructions generated depends on the specific conditional instruction being translated. This parameter change allows optimization of execution efficiency for different instruction types.
Data Source
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AI summary
An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.