Multi-Slice Microprocessor Issue Queue Tag Matching
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Solution Overview
Problem
Traditional processor architectures face inefficiencies in managing speculative load data due to their one-to-one configuration of issue queues, registers, and history buffers, which limits the distribution of writeback data from multiple load store units, leading to suboptimal performance in distributed architectures.
Innovation Solution
A computing system matches writeback instruction tags to entry instruction tags in an issue queue, using multiple ready bits to indicate when writeback data is available from multiple load store units, allowing for the issuance of instructions only when all ready bits are set, enabling efficient data management across distributed components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional one-to-one configuration is used for issue queue, register, and history buffer, then the structure is simple and easy to manage, but the performance is limited due to inability to efficiently handle distributed writeback data from multiple load store units
Solution Approach 1:
The patent segments the writeback data reception capability across multiple load store units, where each unit can independently provide portions of writeback data to the issue queue, register, and history buffer. This segmentation enables parallel data delivery paths, improving instruction issuance efficiency while distributing the data management workload across multiple specialized units rather than relying on a single centralized path.
Solution Approach 2:
The issue queue entries, register entries, and history buffer entries are designed with universal readiness tracking capability through ready bits that can be set by any of the multiple load store units. This multi-functional design allows each entry to receive and track data from multiple sources, enabling the system to efficiently handle distributed writeback data while maintaining a unified interface for instruction issuance.
2Productivity
If load data is written into general purpose register before address translation is known, then performance is improved through speculative execution, but data correctness may be compromised if speculation fails
Solution Approach 1:
The patent implements preliminary action by writing load data into the general purpose register or history buffer before address translation is fully confirmed, enabling speculative execution to proceed without waiting for translation completion. The ready bits mechanism allows the system to prepare and track speculative data early, improving performance while maintaining the ability to validate and correct data if speculation fails.
Solution Approach 2:
The system employs feedback through the ready bits that track the availability and validation status of speculative load data. When address translation is confirmed or data is validated, the corresponding ready bits are set, providing feedback that confirms data correctness. This feedback mechanism allows the system to maintain speculative execution performance while ensuring data reliability through validation confirmation.
Data Source
AI summary
An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.