Microprocessor P-State Transition via Iterative Frequency Control

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Solution Overview

Problem

Conventional methods for increasing microprocessor performance, such as overclocking, are unreliable and inefficient, and existing thermal monitoring mechanisms fail to provide optimal performance and protection, especially during P-state transitions and varying temperature conditions.

Innovation Solution

The microprocessor employs iterative frequency changes and dual phase-locked loops to transition between voltage and frequency states without suspending operation, allowing for dynamic voltage and frequency adjustments based on temperature and workload, optimizing performance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the microprocessor increases its operating voltage to support higher frequency according to physical characteristics, then the frequency can be increased, but the transition time becomes significant and performance is lost during the transition

Engineering Contradiction:
ImprovefrequencyVSAvoidtransition time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The microprocessor performs preliminary frequency adjustment before voltage adjustment during P-state transitions. By iteratively changing the frequency to intermediate values and only suspending operation when voltage changes are required, the system minimizes the time lost during transitions while still adhering to physical constraints that require voltage support for higher frequencies

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The transition from current frequency to destination frequency is divided into multiple iterative steps. The frequency is adjusted in increments toward the destination frequency, with voltage adjustments performed only when necessary to support each frequency level. This segmentation reduces the overall transition time by keeping the processor operational at intermediate frequencies rather than suspending operation for the entire transition duration

Inventive Principle:
Principle #1Segmentation

2Speed

If conventional overclocking is used to increase performance, then the operating frequency can be increased, but the system becomes unreliable and requires additional cooling

Engineering Contradiction:
Improveoperating frequencyVSAvoidoperation reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The microprocessor dynamically adjusts its operating frequency and voltage based on real-time temperature monitoring and workload conditions. The system can operate at higher frequencies when temperature and workload permit, and automatically reduce frequency when thermal limits are approached, providing reliable operation without requiring aggressive cooling systems

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback through temperature sensors that continuously monitor the microprocessor's operating temperature. This feedback enables the system to automatically adjust frequency and voltage to maintain reliable operation within thermal constraints, eliminating the unreliability associated with conventional overclocking while maximizing performance within safe operating limits

Inventive Principle:
Principle #23Feedback

3Productivity

If the microprocessor operates at higher frequency to deliver higher performance, then performance increases, but power consumption increases proportionally to frequency and square of voltage

Engineering Contradiction:
ImproveperformanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system dynamically changes operating parameters (frequency and voltage) based on actual workload requirements and thermal conditions. Rather than operating at maximum frequency and voltage continuously, the microprocessor adjusts these parameters to match the required performance level, thereby reducing power consumption during low-workload periods while maintaining high performance when needed

Inventive Principle:
Principle #35Parameter changes

4Reliability

If thermal monitoring mechanisms are used to protect the microprocessor, then protection is provided, but optimal performance cannot be achieved during P-state transitions and varying temperature conditions

Engineering Contradiction:
Improvethermal protectionVSAvoidperformance during transitions
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The thermal monitoring mechanism works in conjunction with preliminary frequency adjustment before voltage adjustment during P-state transitions. By iteratively changing frequency first, the system can respond to thermal conditions more rapidly while still providing adequate protection, thereby maintaining both reliability and performance during transitions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The thermal monitoring system dynamically adjusts protection thresholds and response characteristics based on operating conditions. Rather than using fixed thermal thresholds that may be overly conservative, the system adapts its protection behavior to match actual workload and environmental conditions, enabling optimal performance while maintaining adequate thermal protection

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP1975761B1Microprocessor with improved performance during P-state transitions
Publication Date: 2017.03.08 VIA TECH INC
  • EP1975761B1 patent drawing
  • EP1975761B1 patent drawing
  • EP1975761B1 patent drawing

AI summary

A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, and a control circuit. The control circuit, in response to a request to operate the core logic at a destination frequency, iteratively controls the clock generation circuitry to generate the core clock signal having a new frequency until the core clock signal frequency is the destination frequency, without suspending operation of the core logic. The new core clock signal frequency on each iteration is one of the N different possible frequencies monotonically closer to the destination frequency. The number of iterations is between zero and N-1 depending upon the destination frequency specified and the core clock signal frequency when the request is received.