Microprocessor Instruction Dispatch for Long-Throughput Pipelines
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Solution Overview
Problem
Existing microprocessors face inefficiencies in executing instructions with long throughput times due to complex dynamic scheduling and resource conflicts, leading to increased power consumption and chip area usage.
Innovation Solution
Implement a microprocessor with a time counter for static instruction dispatching, using a time-resource matrix to schedule instructions based on known throughput and latency times, and incorporate a replay mechanism for delayed result data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic scheduling is used to execute instructions, then instruction execution flexibility is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent pre-calculates and stores optimal scheduling decisions in a lookup table during design time, eliminating the need for complex runtime scheduling logic. The microprocessor directly retrieves scheduling information from the lookup table based on instruction patterns, achieving flexible instruction execution without complex dynamic scheduling mechanisms.
Solution Approach 2:
The patent creates a simplified model of the scheduling problem by pre-computing optimal schedules for various instruction patterns and storing them as lookup tables. This copy of pre-computed solutions allows the processor to execute instructions flexibly by simply retrieving pre-determined scheduling decisions rather than performing complex real-time optimization.
2Productivity
If more functional units are added to increase instruction throughput, then productivity is improved, but chip area increases
Solution Approach 1:
The patent implements dynamic instruction scheduling that allocates functional units based on actual workload requirements rather than providing dedicated units for all possible instruction types. The scheduler dynamically assigns available functional units to pending instructions, allowing the same physical resources to handle diverse instruction patterns efficiently without requiring excessive hardware for each instruction type.
Solution Approach 2:
The patent designs functional units that can execute multiple types of instructions through unified execution pipelines and configurable operation modes. Rather than having separate dedicated units for each instruction type, the same functional units are configured via control signals to perform different operations, reducing the total number of physical units needed while maintaining high instruction throughput.
3Reliability
If instructions with long throughput times are executed using traditional scheduling, then execution completeness is improved, but power consumption and stalling increase
Solution Approach 1:
The patent pre-identifies instructions with long throughput times (such as divide instructions) and pre-determines their scheduling parameters in the lookup table. This allows the processor to handle these instructions efficiently by retrieving pre-optimized scheduling information, avoiding the power consumption and stalling that would result from traditional dynamic scheduling approaches.
Solution Approach 2:
The patent applies specialized scheduling strategies for specific instruction types with known characteristics (like long throughput divide instructions) by storing instruction-specific parameters in the lookup table. This localized optimization ensures that each instruction type, particularly those with unusual timing requirements, receives tailored scheduling treatment that minimizes power consumption and avoids unnecessary stalling while maintaining execution completeness.
Data Source
AI summary
A processor includes a time counter and a time-resource matrix and statically dispatches instructions if the resources are available based on data stored in the time-resource matrix. Execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution of a second instruction to a functional unit may be replayed due to the throughput time of a first instruction to the same functional unit. A busy bit and next available time of the functional unit are set when the first instruction is sent to the functional unit are the indication to replay the second instruction.