Microprocessor Memory Bank Address Translation
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Solution Overview
Problem
Existing microprocessor/microcontroller architectures with banking schemes face limitations in providing a continuous larger memory area, requiring significant additional logic and large memory banks to accommodate special function registers, and do not allow for efficient access to a single continuous memory block.
Innovation Solution
A processor device with a data memory accessible through multiple memory banks, where a subset of banks is organized into first and second memory areas, and an address adjustment unit translates addresses to form a continuous linear memory block, allowing access to special function and general purpose registers as a single continuous memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory banks are organized with separate first and second memory areas for special function registers and general purpose registers, then memory organization flexibility is improved, but the ability to form a continuous linear memory block deteriorates
Solution Approach 1:
An address translation unit is introduced as an intermediary component that translates virtual addresses into physical addresses. This unit maps the non-contiguous physical memory areas (separated into first and second memory areas) to a contiguous virtual address space, allowing the processor to access memory as if it were continuous while maintaining the flexible banked organization physically
Solution Approach 2:
The patent introduces a virtual address space dimension that overlays the physical address space. By organizing memory access through virtual addresses that map to physical locations across multiple banks, the system creates a continuous memory appearance in the virtual dimension while maintaining the segmented physical structure
2Ease of operation
If large memory banks are designed to accommodate all special function registers, then access to special function registers is improved, but device complexity and logic requirements increase significantly
Solution Approach 1:
The memory system is segmented into multiple smaller memory banks, each containing a first memory area for special function registers and a second memory area for general purpose registers. This segmentation allows special function registers to be distributed across multiple banks rather than requiring one large bank, reducing the complexity of any single bank while maintaining easy access through the banking mechanism
Solution Approach 2:
Each memory bank is designed with universal structure containing both first memory area (for special function registers) and second memory area (for general purpose registers). This multi-functional design allows any bank to serve either purpose depending on the address translation, eliminating the need for dedicated large banks for each function
3Adaptability or versatility
If non-consecutive memory blocks are used in memory banks, then memory efficiency and flexibility are improved, but access efficiency to form continuous memory blocks deteriorates
Solution Approach 1:
The address translation unit acts as a mediator that handles the complexity of mapping non-consecutive physical memory blocks to consecutive virtual addresses. By pre-calculating and managing these mappings, the translation unit enables efficient access without requiring the physical memory to be organized in consecutive blocks, thus maintaining both flexibility and access efficiency
Data Source
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AI summary
A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.