Microprocessor Non-Cacheable Load Prediction Mechanism
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Solution Overview
Problem
Traditional out-of-order superscalar microprocessors face challenges in power consumption and design complexity, particularly with dynamic scheduling of instructions, which leads to increased power usage and complexity, especially when dealing with non-cacheable memory data access in AI and machine learning applications.
Innovation Solution
A microprocessor with a time counter for statically dispatching instructions, using a non-cacheable predictor to predict latency times and implement a static scheduling algorithm that schedules instructions based on preset execution times, reducing the need for speculative execution and replay, and employing a prefetch mechanism for non-cacheable loads to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic scheduling of instructions is used in out-of-order superscalar microprocessors, then instruction execution flexibility and throughput are improved, but power consumption and design complexity increase
Solution Approach 1:
The patent segments the scheduling function into static scheduling for non-cacheable loads and dynamic scheduling for cacheable loads. This division allows the complex dynamic scheduling to be used only where necessary (cacheable memory), while simpler static scheduling handles non-cacheable memory access, reducing overall complexity while maintaining throughput.
Solution Approach 2:
The patent implements preliminary action by predicting non-cacheable load instructions before execution and pre-calculating their latency. This allows the static scheduler to prepare execution slots in advance, avoiding the need for complex runtime decision-making and reducing power consumption associated with dynamic scheduling logic.
2Productivity
If speculative execution and replay operations are performed for cache misses, then instruction throughput is improved, but power consumption increases
Solution Approach 1:
The patent inverts the traditional approach by treating non-cacheable loads differently from cacheable loads. Instead of using speculative execution for all loads and replaying on miss, the patent uses static prediction and deterministic scheduling for non-cacheable loads, eliminating the need for speculative execution and associated power consumption.
Solution Approach 2:
The patent extracts non-cacheable load instructions from the general dynamic scheduling pipeline and handles them through a separate static scheduling mechanism. This extraction removes the power-consuming speculative execution and replay operations from the critical path for non-cacheable memory access.
3Device complexity
If all load instructions assume L1 data cache hit latency, then simple latency estimation is achieved, but performance degrades when data is in non-cacheable memory
Solution Approach 1:
The patent applies local quality by providing different latency estimates for different types of load instructions. Cacheable loads use the simple L1 cache hit latency assumption, while non-cacheable loads use a separate prediction mechanism that accounts for their longer external memory access time, optimizing performance for each case.
Solution Approach 2:
The patent changes the latency parameter based on the load type. Instead of using a fixed L1 cache hit latency for all loads, the system dynamically adjusts the latency estimate based on whether the load is predicted to be non-cacheable, allowing accurate timing for both cacheable and non-cacheable memory access.
Data Source
AI summary
A processor includes an instruction issue unit that receives a first instruction, and issues the first instruction with a write time, which for a load instruction corresponds to a data cache latency time or to a non-cacheable latency time of a non-cacheable predictor. The non-cacheable predictor includes a tag array and data array with a plurality of entries to predict non-cacheable latency times of non-cacheable load instructions. The non-cacheable predictor can be implemented as a direct map, an N-way associative cache, or a fully associative cache.