Microprocessor-PLD Bus Controller for Low-Latency IPC Transfer
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Solution Overview
Problem
The complexity of interconnecting programmable logic device (PLD) building blocks for different applications restricts modularity, re-use, and increases costs due to the need for frequent modifications, complicating the development and maintenance of PLD architectures.
Innovation Solution
A microprocessor-PLD hybrid architecture that includes a bus controller module capable of executing a command sequence, allowing for high-data integrity and robust command-data exchange between multiple PLD modules via an IPC interface, with the bus controller transferring data and executing commands at a higher rate than the IPC interface, enabling efficient communication and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PLD building blocks are interconnected for different applications, then functionality and adaptability are improved, but complexity of interconnection and device complexity increase
Solution Approach 1:
The bus controller is designed with a universal architecture that can manage multiple PLD modules through a standardized bus interface. The controller executes bus controller instructions to handle data transfer operations across different PLD modules, allowing the same hardware structure to serve multiple applications without requiring custom interconnection designs for each case.
Solution Approach 2:
The system separates the control functionality from the data storage functionality by introducing a dedicated bus controller module. The controller handles all interconnection management, command execution, and data transfer operations, while PLD modules can be independently configured for specific functions. This segmentation reduces interconnection complexity by centralizing control logic.
2Adaptability or versatility
If PLD architecture is modified for different applications, then adaptability is improved, but manufacturing cost and ease of manufacture worsen
Solution Approach 1:
The bus controller implements a universal command execution mechanism that can adapt to different PLD module configurations through software instructions rather than hardware modifications. The controller reads and executes bus controller instructions stored in memory, allowing the same manufactured device to be reconfigured for different applications without requiring physical changes or additional manufacturing steps.
Solution Approach 2:
The system uses dynamically loadable bus controller instructions that can be programmed and modified during operation. The controller fetches instructions from memory and executes them sequentially, allowing the functionality to change adaptively without hardware reconfiguration. This dynamic approach enables a single manufactured device to serve multiple applications.
3Productivity
If bus controller executes commands at high rate, then productivity is improved, but complexity of control and device complexity increase
Solution Approach 1:
The bus controller operates by periodically fetching and executing bus controller instructions from memory in a sequential manner. This periodic instruction execution model simplifies the control logic compared to complex event-driven or interrupt-based systems, as the controller follows a predictable fetch-decode-execute cycle that can be implemented with straightforward hardware state machines while maintaining high execution rates.
4Reliability
If IPC interface uses more command bits, then reliability is improved, but loss of information and productivity worsen
Solution Approach 1:
The system implements acknowledgment mechanisms where the bus controller and PLD modules exchange status information to confirm successful data transfer operations. The controller can verify that instructions were executed correctly and that data was transferred reliably, providing feedback that ensures data integrity without requiring excessive command bits in the IPC interface.
Data Source
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AI summary
A microprocessor-PLD hybrid architecture includes an IPC microprocessor (102) and a PLD (150) in signal communication with the IPC microprocessor (102) via an IPC interface (104). The IPC microprocessor (102) outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules (154a-154n) that store data and a bus controller (152). The bus controller (152) communicates with the plurality of PLD modules (154a-154n) via a plurality of PLD interfaces (170) and is configured to sequentially execute a set of bus controller instructions (166). The bus controller (152) reads data from a target PLD module from among the plurality of PLD modules (154a-154n) in response to receiving the data read command, and transfers the data to the IPC microprocessor (102). The bus controller (152) receives data from the IPC microprocessor (102) and stores the data in a target PLD module from among the plurality of PLD modules (154a-154n) in response to receiving the data write command.