Microprocessor Repeat Prefetch Indirect Instruction
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Solution Overview
Problem
Existing prefetch instructions for microprocessors require multiple sequential prefetch instructions to load non-sequential cache lines, increasing code size and processor execution, which is inefficient.
Innovation Solution
A new prefetch instruction, REP PREFETCH INDIRECT, allows specifying multiple non-sequential cache lines through a prefetch table with address operands and a count, enabling efficient prefetching of cache lines by calculating addresses from the table entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple sequential prefetch instructions are used to load non-sequential cache lines, then the cache lines can be prefetched, but the code size increases and processor execution becomes more complex
Solution Approach 1:
The patent introduces a prefetch table as an intermediary data structure that stores pointers to cache line addresses. Instead of using multiple individual prefetch instructions, a single REP PREFETCH instruction operates on this table, where each entry contains a pointer to a cache line. The processor iterates through the table entries and prefetches the corresponding cache lines, thereby reducing code size and execution complexity while maintaining the ability to prefetch non-sequential cache lines.
2Quantity of substance
If multiple prefetch instructions are used to handle non-sequential cache lines, then all required cache lines can be loaded, but the number of instructions to execute increases
Solution Approach 1:
The patent merges multiple individual prefetch instructions into a single REP PREFETCH instruction that operates on a prefetch table. The instruction takes a pointer to the first entry of the prefetch table and a count of entries, then iterates through all entries in the table, prefetching each indicated cache line. This consolidation reduces the number of instructions the processor must decode and execute, improving productivity while maintaining the ability to prefetch multiple non-sequential cache lines.
Data Source
AI summary
A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, each including a prefetch address. The repeat prefetch indirect instruction also includes a count specifying a number of cache lines to be prefetched. The memory address of each of the cache lines is specified by the prefetch address in one of the entries in the prefetch table. A count register, initially loaded with the count specified in the prefetch instruction, stores a remaining count of the cache lines to be prefetched. Control logic fetches the prefetch addresses of the cache lines from the table into the microprocessor and prefetches the cache lines from the system memory into a cache memory of the microprocessor using the count register and the prefetch addresses fetched from the table.