Microprocessor Private Microcode RAM Storage Architecture
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Solution Overview
Problem
Modern microprocessors face a challenge in providing additional storage for microcode that is fast and consumes less chip area, as traditional user-accessible registers are limited and using system memory is inefficient due to latency and management issues.
Innovation Solution
Incorporating a denser but slower private random access memory (PRAM) within a non-user-accessible address space, accessible only by microcode, which allows for efficient data storage and retrieval through specific microinstructions, reducing the need for additional user-accessible registers and minimizing system memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional user-accessible registers are added to provide storage for microcode, then storage capacity is improved, but chip area consumption increases
Solution Approach 1:
The patent segments the storage system into two distinct parts: user-accessible registers and a private memory space accessible only by microcode. This segmentation allows the microcode to have dedicated storage without increasing the user-visible register count, thereby providing additional storage capacity while avoiding proportional increases in chip area consumption for user-facing resources.
Solution Approach 2:
The patent introduces a private memory intermediary between the microcode and the user-accessible registers. This intermediary storage space is managed separately from the user register file, allowing microcode operations to access additional storage without directly expanding the user-accessible register set, thus resolving the contradiction between storage capacity and chip area.
2Quantity of substance
If system memory is used for additional storage space, then storage capacity is improved, but access latency increases
Solution Approach 1:
The patent creates a new dimension of storage by introducing a private memory space that exists alongside but separate from both user-accessible registers and system memory. This intermediate storage layer provides microcode with dedicated storage that is faster than system memory while not competing with user register access, effectively adding storage capacity without the latency penalty of system memory access.
3Quantity of substance
If system memory is used for additional storage, then storage capacity is improved, but memory management complexity increases
Solution Approach 1:
The patent extracts the microcode storage management function from the general system memory management domain. By creating a private memory space that is exclusively allocated to and managed by microcode operations, the system removes the complexity of OS-managed memory allocation and dealing with system memory latency from the microcode execution path, thereby improving both storage capacity and management simplicity.
Data Source
AI summary
A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR.