Microprocessor Reciprocal Square Root Acceleration

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Solution Overview

Problem

Conventional microprocessors face challenges in accelerating computations, particularly in ray casting for VR, AR, and XR applications, due to high latency and power consumption, and limitations in binary32 format leading to issues with square root computations and dynamic range limitations.

Innovation Solution

The implementation of reciprocal or reciprocal square root instructions that generate significand with high precision and unbounded exponents to accelerate numerical computations, allowing for faster division and square root operations by modifying mathematical equations to handle edge cases such as zero and infinity inputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If Newton-Raphson or SRT algorithms are used for division and square root computation, then computation accuracy is maintained, but computation speed is slow due to iterative and recurrent natures

Engineering Contradiction:
Improvecomputation speedVSAvoidcomputation time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-computing reciprocal square root values for a table of input values and storing them in a lookup table. During actual computation, the system only needs to perform table lookup and multiplication operations instead of executing slow iterative algorithms, significantly reducing computation time while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a lookup table that copies pre-computed reciprocal square root values for various input operands. This allows the system to retrieve approximate reciprocal square root values quickly without performing complex real-time calculations, thereby accelerating the overall computation speed.

Inventive Principle:
Principle #26Copying

2Speed

If reciprocal square root equation (X*R) is applied to compute square root, then computation speed increases, but incorrect results are generated for edge cases like zero input

Engineering Contradiction:
Improvecomputation speedVSAvoidcomputation correctness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements feedback by checking whether the input operand is zero before applying the reciprocal square root computation. When zero is detected, the system provides a special handling path that returns zero as the correct square root result, preventing the generation of incorrect NaN values while maintaining the fast computation path for non-zero inputs.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies beforehand cushioning by detecting edge cases (zero input) in advance and preparing appropriate handling responses before the main computation executes. This prevents errors from propagating through the computation pipeline and ensures correct results for boundary conditions.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Quantity of substance

If binary32 format is used for numerical representation, then memory usage is reduced, but dynamic range is limited causing underflow and overflow issues

Engineering Contradiction:
Improvememory usageVSAvoiddynamic range
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent changes the parameter of exponent representation from bounded (binary32 format with exponents in [-126, 127]) to unbounded. By using unbounded exponents, the system can represent numbers with much larger dynamic range, avoiding underflow and overflow issues while maintaining efficient memory usage through the optimized representation format.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240272871A1System and method to accelerate microprocessor operations
Publication Date: 2024.08.15 ARITH INC
  • US20240272871A1 patent drawing
  • US20240272871A1 patent drawing
  • US20240272871A1 patent drawing

AI summary

Systems and methods are directed to accelerating operations associated with a microprocessor. Example embodiments improve the operations of the microprocessor by providing devices (e.g., integrated circuits, independent accelerators) configured to use reciprocal or reciprocal square root instructions. Such devices can be further configured to follow the reciprocal or reciprocal square root instructions with multiplication or other instructions to finish division, square root, or other complex operations.