Microprocessor Reset Bus Architecture for Chip Space Reduction

Solution Overview

Problem

The complexity of microprocessor design is increased by the need for thousands of wires to transmit reset control signals, consuming valuable space and requiring careful design to avoid power domains, making it difficult to manufacture high-performance computing systems in small packages.

Innovation Solution

A reset communication bus is introduced to transmit reset control messages and receive response messages, allowing each logic portion of the microelectronic circuit to execute commands and reduce the number of wires needed, with branching configurations to accommodate power domains and simultaneous transmission of inbound and outbound signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thousands of wires are used to transmit reset control signals from the reset controller to all components, then the reset control function is achieved, but the chip space is consumed and the design complexity increases

Engineering Contradiction:

Improvereset control functionVSAvoidchip space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the reset control function into the existing clock distribution network by integrating reset control logic with clock buffer circuits. The reset controller uses the same physical infrastructure (clock trees, buffer circuits) to distribute reset signals, thereby eliminating the need for separate dedicated reset wires throughout the chip.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The clock distribution network is made multi-functional by enabling it to carry both clock signals and reset control signals through the same physical pathways. The buffer circuits serve dual purposes: clock buffering and reset signal generation/distribution, maximizing the utility of existing chip infrastructure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If thousands of wires are used to transmit reset control signals, then the reset control function is achieved, but the design and manufacturing difficulty increases

Engineering Contradiction:

Improvereset control functionVSAvoiddesign and manufacturing difficulty

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the reset control function into the existing clock distribution network by integrating reset control logic with clock buffer circuits. The reset controller uses the same physical infrastructure (clock trees, buffer circuits) to distribute reset signals, thereby eliminating the need for separate dedicated reset wires throughout the chip.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The clock buffer circuits serve as intermediaries that receive control signals from the reset controller and generate appropriate reset outputs. This intermediary layer simplifies the interface between the reset controller and various chip components, reducing design complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If reset control wires are designed around power domains to avoid interactions, then power domain isolation is maintained, but the wire routing complexity and space consumption increase

Engineering Contradiction:

Improvepower domain isolationVSAvoidwire routing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The clock buffer circuits serve as intermediaries that receive control signals from the reset controller and generate appropriate reset outputs. This intermediary layer simplifies the interface between the reset controller and various chip components, reducing design complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The reset control system uses the existing clock distribution infrastructure to serve its own signal distribution needs, eliminating the requirement for separate reset wire routing that would need to navigate around power domains.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9864604B2Distributed mechanism for clock and reset control in a microprocessor

Publication Date: 2018.01.09 ORACLE INT CORP

AI summary

Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.