Microprocessor Retire Unit Early Instruction Retirement

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Solution Overview

Problem

The size of the reorder buffer (ROB) in superscalar microprocessors limits the lookahead capability and utilization of execution units, as each entry requires significant hardware resources and increasing its size is costly.

Innovation Solution

Implementing a microprocessor with a small in-order instruction retirement buffer that selectively initiates instruction retirement early for non-excepting instructions, allowing earlier freeing of ROB entries and improving execution unit utilization without increasing buffer size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the size of the reorder buffer (ROB) is increased to improve lookahead capability and execution unit utilization, then the processor can keep more instructions ready for execution, but each additional ROB entry consumes significant hardware resources and power

Engineering Contradiction:
Improveexecution unit utilizationVSAvoidROB size
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by determining whether an instruction can be retired before its execution result is produced. The retire unit checks if the oldest instruction in the ROB is ready for retirement in advance, allowing the ROB entry to be freed earlier than traditional approaches. This early determination enables subsequent instructions to be allocated to freed entries without waiting for full execution completion, thereby improving execution unit utilization without increasing ROB size.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the ROB size is increased to allow more instructions to be ready for execution, then lookahead capability improves, but the hardware cost and power consumption increase significantly

Engineering Contradiction:
Improvelookahead capabilityVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements preliminary action by performing retirement determination ahead of traditional retirement timing. The retire unit evaluates whether the oldest instruction can be retired before its result is produced, freeing ROB entries earlier than conventional methods. This advance freeing capability increases the number of instructions that can be held ready for execution, thereby improving lookahead capability without requiring additional hardware resources.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If instructions are retired only after execution completion to ensure correctness, then reliability is maintained, but execution unit utilization decreases due to delayed ROB entry freeing

Engineering Contradiction:
Improveinstruction retirement correctnessVSAvoidexecution unit utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating retirement handling based on instruction type. Excepting instructions (those that can cause exceptions) follow traditional retirement timing after result production to maintain reliability. Non-excepting instructions (those incapable of causing exceptions) are retired early based on preliminary determination, improving execution unit utilization. This selective approach allows the system to optimize different instruction types with appropriate retirement strategies.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by modifying the retirement timing parameter based on instruction characteristics. Instead of a fixed retirement timing for all instructions, the system changes the retirement parameter (timing) according to whether an instruction is excepting or non-excepting. This parameter adaptation enables early retirement of safe instructions while maintaining traditional timing for instructions requiring stricter verification, thereby improving overall execution unit utilization without compromising reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8074060B2Out-of-order execution microprocessor that selectively initiates instruction retirement early
Publication Date: 2011.12.06 VIA TECH INC
  • US8074060B2 patent drawing
  • US8074060B2 patent drawing
  • US8074060B2 patent drawing

AI summary

A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result. The retire unit makes the determination before the execution unit outputs the result of the non-excepting type instruction, wherein the retire unit makes the determination after the execution unit outputs the result of the excepting type instruction.