Microprocessor Shared Memory Bus Arbitration
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Solution Overview
Problem
Current microprocessors are limited in sharing circuits between von Neumann and Harvard types, leading to inefficiencies such as increased circuit scale and power consumption due to the need for separate memory buses and arbitration circuits, which hinder performance and flexibility.
Innovation Solution
A microprocessor design that includes a first and second memory bus, a fetch part, a bus controller, and a determination part to manage access between the buses, allowing for shared circuit operation between von Neumann and Harvard types without the need for a bus arbitration circuit, enabling simultaneous access to program and data memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional Harvard type processor uses two memory buses to access program and data memory simultaneously, then access speed is improved, but circuit scale increases due to the need for separate buses and arbitration circuits
Solution Approach 1:
The patent merges the program bus and data bus into a single shared memory bus, allowing both program and data memory to share the same physical bus infrastructure. This eliminates the need for separate bus circuits while maintaining simultaneous access capability through logical arbitration at the controller level rather than requiring dedicated hardware arbitration circuits for each bus.
Solution Approach 2:
The memory bus is designed with universal functionality to handle both program memory access and data memory access through a single bus interface. The bus controller can dynamically allocate the bus for different purposes (program fetch or data access) based on operational needs, making the single bus serve multiple functions that traditionally required separate dedicated buses.
2Adaptability or versatility
If a bus arbitration circuit is added to improve flexibility of memory usage in Harvard type processors, then adaptability is improved, but power consumption increases due to continuous arbitration operations
Solution Approach 1:
The bus arbitration operates periodically based on access requests rather than continuously. The arbitration logic is activated only when needed to allocate the shared bus between program and data access operations, and remains inactive during periods when the bus is not being contested, thereby reducing overall power consumption while maintaining flexibility.
Solution Approach 2:
The bus controller incorporates self-service arbitration capabilities where the controller automatically manages bus allocation without requiring external arbitration circuits. The controller can autonomously determine when program or data access should use the bus based on its internal state and request signals, eliminating the need for separate power-consuming arbitration hardware.
3Adaptability or versatility
If a bus arbitration circuit is implemented in Harvard type processors, then memory access flexibility is improved, but memory access delay increases due to arbitration processing time
Solution Approach 1:
The bus controller performs preliminary allocation of the shared memory bus based on predicted access patterns and current operational state. By pre-configuring bus allocation decisions before actual access requests occur, the system minimizes arbitration delay while maintaining flexibility. The controller can anticipate when program or data access will be needed and prepare the bus allocation in advance.
4Productivity
If separate memory buses are used in Harvard type processors, then simultaneous program and data access is enabled, but chip area increases due to larger circuit scale
Solution Approach 1:
The patent combines two separate memory buses into one shared memory bus, reducing the physical circuit area required for bus infrastructure. The shared bus uses the same physical transmission lines and control logic for both program and data access, eliminating redundant circuitry while maintaining the capability for simultaneous access through time-multiplexed or arbitrated bus allocation.
Data Source
AI summary
A microprocessor includes: a first memory bus; a second memory bus; a fetch part configured to fetch an instruction from a first memory connected to the first memory bus; a bus controller configured to control the second memory bus; a determination part configured to determine whether or not an address output from the bus controller is in an area of the first memory; and a first logic circuit part configured to use an output of the determination part to set an access destination of the first memory as the bus controller when the address output from the bus controller is in the area of the first memory.