Microprocessor Static Instruction Dispatch via Time Counter
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Solution Overview
Problem
Current microprocessors face challenges in power consumption, design complexity, and performance due to dynamic scheduling of instructions, particularly with high latency load instructions, which complicates speculative execution and replay processes.
Innovation Solution
A microprocessor design that employs a time counter for statically dispatching instructions based on preset execution times, using a time-resource matrix to manage resource availability and a register scoreboard for tracking write-back times, allowing for simpler and more efficient speculative execution and replay mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic scheduling of instructions is used in out-of-order superscalar microprocessors, then instruction execution performance is improved, but power consumption and design complexity increase
Solution Approach 1:
Instead of dynamically scheduling instructions based on real-time resource availability and dependencies, the patent inverts the approach by using a static scheduling method where instructions are issued in a predetermined order based on their sequence number. The execution unit dynamically adapts to resource availability rather than the scheduler adapting to complex dependency resolution, simplifying the overall system architecture while maintaining performance.
Solution Approach 2:
The patent extracts the complex dynamic scheduling logic from the execution pipeline by introducing a separate static scheduler that operates independently. The scheduler simply issues instructions based on their sequence number, while the execution unit handles all dynamic aspects of resource allocation and dependency resolution, separating the simple scheduling function from the complex execution function.
2Productivity
If load instructions with high latency are prioritized in the execution pipeline, then load-dependent instructions can execute sooner, but speculative execution and replay complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the sequence numbers of instructions in the instruction stream before execution. This allows the static scheduler to issue instructions in the correct order without needing to dynamically track dependencies or manage complex replay scenarios. The sequence number information is prepared in advance, eliminating the need for complex speculative execution and replay mechanisms.
Solution Approach 2:
The sequence number acts as an intermediary mechanism that mediates between the simple static scheduler and the complex execution unit. Instead of the scheduler needing to understand complex dependencies or manage speculative execution, the sequence number provides a simple ordering mechanism that the execution unit uses to manage instruction issuance, thereby simplifying the scheduler while maintaining execution correctness.
3Productivity
If selective replay of dependent instructions is implemented, then performance is improved, but scheduling complexity increases significantly
Solution Approach 1:
The execution unit performs self-service by automatically handling dependency resolution and instruction replay based on the sequence numbers provided by the static scheduler. The execution unit monitors resource availability and instruction dependencies, and when a load instruction misses, it automatically replays dependent instructions without requiring complex scheduling logic or external intervention. This shifts the complexity from the scheduler to the execution unit, which is better positioned to handle such dynamic aspects.
Data Source
AI summary
A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching instructions if the resources are available based on data stored in the time-resource matrix, and wherein execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction and subsequent dependent instructions to be statically replayed at a later time using the same time count.