Microprocessor Selective Substrate Biasing Leakage Reduction
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Solution Overview
Problem
Sub-threshold leakage current in CMOS microprocessors contributes significantly to power consumption and noise, particularly in functional blocks that are not in use, as conventional substrate biasing methods do not allow for selective reduction of leakage in specific areas.
Innovation Solution
A microprocessor design with selective substrate biasing that includes a substrate bias rail and logic to clamp the rail to core voltages during full power mode and drive it to offset voltages during low power mode, using charge nodes and select logic to minimize leakage and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If substrate biasing is applied to reduce sub-threshold leakage current, then power consumption is reduced, but device complexity increases due to additional bias generators and control circuitry
Solution Approach 1:
The microprocessor is divided into multiple independently controllable functional blocks, each with its own substrate biasing control. This allows selective application of substrate biasing to only those blocks that need power reduction, rather than applying it globally to the entire device, thus reducing the overhead complexity while maintaining power savings.
Solution Approach 2:
The substrate biasing system is made dynamic through clock-gated control, where the substrate bias is selectively applied based on whether functional blocks are active or idle. This dynamic control allows the system to adapt substrate biasing to real-time operational needs, reducing unnecessary complexity when power savings are not required.
2Loss of energy
If substrate biasing is applied to reduce sub-threshold leakage current, then leakage current is reduced, but noise on device substrates increases due to voltage variations
Solution Approach 1:
The substrate biasing is segmented to individual functional blocks rather than applied globally. This isolation prevents noise from propagating across the entire substrate, confining voltage variations to only those blocks undergoing biasing transitions, thereby reducing overall noise impact on the device.
Solution Approach 2:
The substrate biasing is applied in a controlled manner with preliminary clamping to ensure stable voltage levels before functional blocks become active. This preliminary stabilization prevents abrupt voltage transitions that could generate noise, allowing leakage reduction without significant noise penalty.
3Productivity
If selective substrate biasing is implemented for clock-gated functional blocks, then power management is optimized, but device complexity increases due to additional select logic and control circuitry
Solution Approach 1:
The substrate biasing control is merged with the existing clock-gating control infrastructure of the microprocessor. By reusing the same control signals and logic that already manage clock distribution to functional blocks, the patent avoids duplicating control circuitry, thereby reducing the additional complexity overhead while achieving optimized power management.
Solution Approach 2:
The substrate biasing control circuitry is designed to be universal and multi-functional, serving both power management and noise reduction purposes simultaneously. The same control logic that manages substrate biasing also coordinates with clock-gating signals, allowing a single control mechanism to handle multiple aspects of power optimization without requiring separate dedicated circuitry for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces sub-threshold leakage current and power consumption by selectively biasing semiconductor devices, minimizing voltage variations and noise, thereby improving operational efficiency and performance.
Implementation Method 1
Sub-threshold leakage current is the current that flows between the drain and source when the gate-to-source voltage is below the threshold voltage of the CMOS device. The substrate bias logic charges the first charge node to a first bias voltage at a first offset voltage relative to the first core voltage when the functional block is in the low power mode.
Implementation Method 2
The first select logic couples the first substrate bias rail to the first charge node when the functional block is in a low power mode and clamps the first substrate bias rail to the first supply node when the functional block is in a full power mode.
Data Source
AI summary
A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.