Multithreading Microprocessor Thread Scheduler Pipeline Flush

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Solution Overview

Problem

In multithreaded microprocessors, stalled execution pipelines waste instruction execution bandwidth due to stalling events, as all threads are affected even if only one thread is stalled, leading to inefficiencies in clock cycle utilization.

Innovation Solution

A multithreading processor detects stalling events and flushes only the stalling thread, allowing other threads' instructions to continue executing, thereby avoiding pipeline bubbles and optimizing pipeline utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all threads are flushed when one thread stalls, then pipeline correctness is maintained, but pipeline utilization efficiency deteriorates

Engineering Contradiction:
Improvepipeline correctnessVSAvoidpipeline utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the pipeline flush operation by thread, allowing individual thread contexts to be flushed independently rather than flushing all threads. This is achieved through separate flush control logic for each thread context, enabling selective flushing that maintains correctness while improving utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by making the flush operation thread-specific rather than global. Each thread context has its own flush state and control mechanisms, allowing the system to apply flushing only where necessary (for stalled threads) while preserving execution continuity for active threads.

Inventive Principle:
Principle #3Local quality

2Reliability

If the execution pipeline stalls for one thread, then instruction execution correctness is maintained, but clock cycle utilization deteriorates

Engineering Contradiction:
Improveinstruction execution correctnessVSAvoidclock cycle utilization
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic thread context switching during pipeline execution. When a stall is detected in one thread, the system dynamically switches to executing instructions from other ready threads, making the pipeline execution adaptive and responsive to stall conditions rather than static and rigid.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The thread scheduler acts as an intermediary that mediates between the execution pipeline and multiple thread contexts. It detects stalls, determines which threads can proceed, and coordinates the switching of execution to maintain correctness while minimizing time loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple threads share functional units concurrently, then instructions per clock cycle increases, but resource conflict complexity increases

Engineering Contradiction:
Improveinstructions per clock cycleVSAvoidresource conflict complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action through the thread scheduler that pre-determines thread execution order and resource allocation before actual execution occurs. By scheduling threads in advance and predicting resource needs, the system resolves conflicts proactively rather than reactively, reducing operational complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7657891B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
Publication Date: 2010.02.02 MIPS TECH INC
  • US7657891B2 patent drawing
  • US7657891B2 patent drawing
  • US7657891B2 patent drawing

AI summary

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.