Microprocessor Static Dispatch via Time Counter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current superscalar microprocessors face challenges in efficiently extending their instruction sets, consuming excessive power, and having complex designs due to dynamic scheduling and increased components, which limits scalability and performance.
Innovation Solution
A register scoreboard with a time counter is used for statically dispatching instructions to an execution pipeline based on preset execution times, eliminating the need for dynamic scheduling and reducing complexity by ensuring instructions are executed only when all dependencies are resolved and resources are available, thus allowing for efficient execution of both baseline and extended instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic scheduling is used in superscalar microprocessors to improve instruction execution flexibility, then instruction dispatch adaptability is improved, but device complexity and power consumption increase dramatically
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing dispatch times for all instructions in a schedule table before execution. The dispatch time for each instruction is determined in advance based on data dependencies and resource availability, eliminating the need for complex real-time dynamic scheduling decisions during instruction execution. This transforms the scheduling problem from a complex runtime decision-making process into a simple time-based lookup operation.
2Adaptability or versatility
If extended instruction sets are added to improve specialized application performance, then processing capability is improved, but device complexity and area increase dramatically
Solution Approach 1:
The patent applies universality by designing a unified static scheduling mechanism that handles both baseline and extended instructions through the same time counter and schedule table infrastructure. The execution pipeline remains fundamentally the same, with the static dispatching system providing a universal control mechanism that works across different instruction types without requiring separate complex control logic for each instruction set extension.
Solution Approach 2:
The patent applies parameter changes by using the time counter value as a key parameter to control instruction dispatch. Instead of using complex control signals and status flags, the system changes the dispatch timing parameter based on pre-calculated schedule table entries, allowing extended instructions to be integrated seamlessly by simply updating their dispatch time parameters rather than adding complex control logic.
3Productivity
If more instructions are issued per clock cycle to improve performance, then productivity is improved, but power consumption and area increase due to saturation
Solution Approach 1:
The patent applies preliminary action by pre-determining the optimal issue time for each instruction in the schedule table before execution. The time counter systematically increments and triggers dispatch at pre-calculated times, allowing multiple instructions to be issued per clock cycle in a controlled manner without requiring complex real-time arbitration logic, thereby improving productivity while keeping power consumption manageable.
Data Source
AI summary
A processor includes a time counter and a register scoreboard and provides a method for statically dispatching custom or extended instructions with preset execution times based on a write time of a register in the register scoreboard and the time counter provided to an execution pipeline.