Microprocessor Time-Resource Matrix for Static Instruction Dispatch
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Solution Overview
Problem
Current out-of-order superscalar microprocessors face challenges with high power consumption and complex design, while alternative VLIW processors have diminished interest due to complexity and weak performance, necessitating a more efficient and scalable solution.
Innovation Solution
A microprocessor design incorporating a time counter for static instruction scheduling, where instructions are dispatched based on preset execution times, eliminating the need for dynamic scheduling and reducing resource arbitration complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order superscalar microprocessor design is used to achieve high performance, then processing speed is improved, but power consumption and device complexity increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing instruction issue times in a scoreboard before execution. The scoreboard records the optimal issue time for each instruction based on data dependency analysis, allowing the instruction issue unit to simply retrieve and execute instructions at predetermined times rather than dynamically arbitrating complex resource conflicts in real-time.
Solution Approach 2:
The patent segments the instruction execution process into distinct phases: instruction fetch, scoreboard lookup for issue time determination, and execution at the predetermined time. This segmentation separates the complex dependency resolution from the execution control, simplifying the overall system architecture while maintaining out-of-order execution capability.
2Productivity
If out-of-order superscalar microprocessor design is used to achieve high performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The scoreboard performs preliminary action by pre-determining instruction issue times during instruction decode, avoiding the need for complex real-time dynamic scheduling and resource arbitration that would consume additional power during execution. The predetermined issue times are stored and retrieved without requiring intensive computational resources.
3Adaptability or versatility
If dynamic scheduling is implemented to manage resource allocation, then instruction execution flexibility is improved, but device complexity and power consumption increase
Solution Approach 1:
The scoreboard performs preliminary scheduling action by calculating optimal issue times for all instructions before execution begins. This pre-computed scheduling information is stored in the scoreboard, eliminating the need for complex real-time dynamic scheduling logic during instruction execution while maintaining flexibility through out-of-order processing.
Solution Approach 2:
The scoreboard acts as an intermediary between instruction decode and execution units. It stores predetermined issue times and provides this scheduling information to the instruction issue unit, mediating the resource allocation decisions without requiring complex real-time arbitration logic in the execution path.
4Productivity
If more functional units and resources are added to increase throughput, then processing capacity is improved, but device complexity and chip area increase
Solution Approach 1:
The scoreboard performs preliminary action by pre-determining the exact issue time for each instruction based on data dependency resolution. This allows instructions to be efficiently staged and issued to functional units without requiring excessive buffering or complex arbitration logic, improving throughput while controlling the growth of chip area.
Data Source
AI summary
A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching instructions if the resources are available based on data stored in the time-resource matrix, and wherein execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline.