Microprocessor Validation with Random Test Functions and Thread Scheduling
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Solution Overview
Problem
Current microprocessor validation methods face inefficiencies in execution time and resource usage due to skewed test generation and large test package sizes, leading to long load times and cache saturation, especially on hardware.
Innovation Solution
A method utilizing random generated test functions with a user-level scheduler that creates actionable items in system memory, employs a Hardware Thread Table Structure and Process Table Structure, and uses a re-entrant entry point function to execute these items without context switching, allowing for efficient execution across multiple hardware threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large test packages are generated offline and executed, then test coverage is increased, but execution time and load time increase significantly
Solution Approach 1:
The patent divides large test packages into smaller, manageable test cases that can be executed individually or in small batches. This segmentation allows the validation tool to process tests in manageable chunks, reducing overall execution time while maintaining comprehensive coverage through systematic generation of multiple test cases.
Solution Approach 2:
The patent implements preliminary actions by generating and preparing test cases in advance using formal methods, then executing them systematically. The test cases are pre-generated with expected results, allowing for efficient validation without repeated regeneration during execution phases.
2Reliability
If test packages are executed for long durations to achieve comprehensive coverage, then validation thoroughness is improved, but hardware resources become saturated
Solution Approach 1:
The patent applies local quality by targeting specific validation aspects with specialized test cases rather than applying uniform testing across all functions. This allows concentrated validation effort on critical paths while avoiding unnecessary saturation of hardware resources through selective, focused testing.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting test execution parameters such as instruction mix, coverage thresholds, and validation depth based on hardware state and validation progress. This adaptive approach maintains validation thoroughness while preventing hardware saturation by adjusting workload intensity in real-time.
3Manufacturing precision
If formal methods are used for test generation, then test quality is improved, but generation time increases
Solution Approach 1:
The patent implements preliminary action by using formal methods to generate high-quality test cases in advance during the design phase. The test cases are pre-computed with expected results using formal verification techniques, then executed efficiently during validation without requiring time-consuming regeneration or complex runtime analysis.
Solution Approach 2:
The patent uses copying by creating test cases that replicate and vary critical code paths and execution scenarios. Multiple test cases are generated that copy the structure of critical operations with different inputs and conditions, allowing comprehensive validation through repeated execution of validated patterns rather than exhaustive formal verification during runtime.
Data Source
AI summary
A method of microprocessor validation includes creating a plurality of actionable items in a system memory for execution by multiple hardware threads, creating a hardware thread table structure in the system memory, wherein the hardware thread table structure contains the multiple hardware threads, creating a Process Table Structure (PTS) table in the system memory, where the PTS table includes entry points into the plurality of actionable items, creating a re-entrant entry point function (FSCHED) in the system memory to allow the multiple hardware threads to enter the plurality of actionable items, inspecting each of actionable items to identify an inactive actionable item, where if an inactive actionable item is identified, the FSCHED atomically locks the inactive actionable item and a hardware thread enters the inactive actionable item and executes the inactive actionable item until finished, where the FSCHED locks the inactive actionable item and continues searching for inactive actionable items.