Microsector Logic Fabric for Fine-Grained FPGA Reconfiguration
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Solution Overview
Problem
Programmable logic devices face inefficiencies due to large sector-based allocations in logic fabric, leading to over-allocation of resources and increased configuration times, particularly during partial reconfigurations and single-event upset detection.
Innovation Solution
Implementing a microsector architecture with smaller data registers and rearranged interconnections to enable finer granularity in resource allocation, allowing for parallel configuration and reducing the need for read-modify-write operations during partial reconfigurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If large sector-based registers are used in logic fabric, then resource allocation is simplified, but resource utilization efficiency deteriorates due to over-allocation
Solution Approach 1:
The patent divides the logic fabric into smaller microsectors instead of using large sector-based registers. Each microsector contains smaller registers that can be independently allocated, enabling fine-grained resource allocation. This segmentation allows the logic fabric to be divided into manageable units that can be efficiently assigned to different circuit design functions, eliminating the over-allocation problem caused by large sector registers.
2Device complexity
If large sector-based registers are used in logic fabric, then configuration operations are simplified, but configuration time increases particularly during partial reconfigurations
Solution Approach 1:
The logic fabric is segmented into multiple small microsectors with individual registers, allowing parallel configuration operations. Instead of configuring one large sector at a time, multiple microsectors can be configured simultaneously, significantly reducing the overall configuration time. This is particularly beneficial for partial reconfigurations where only specific microsectors need to be updated.
Solution Approach 2:
The patent enables partial reconfiguration by allowing configuration operations to be performed on individual microsectors or subsets of microsectors rather than requiring full logic fabric reconfiguration. This partial action approach reduces configuration time by only updating the necessary portions of the logic fabric while leaving other microsectors operational.
3Productivity
If smaller microsector allocations are implemented, then resource utilization improves, but device complexity increases due to rearranged interconnections
Solution Approach 1:
The patent merges multiple small microsectors to form larger logical regions when needed, allowing flexible aggregation of fine-grained units. This merging capability enables the system to achieve both fine-grained allocation (when individual microsectors are used) and coarse-grained management (when multiple microsectors are grouped), balancing resource utilization efficiency with manageable interconnection complexity.
Data Source
AI summary
Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.