Multi-Layer Microshells for CMOS-Compatible Vacuum Encapsulation
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Solution Overview
Problem
Conventional microshells for encapsulating microelectromechanical systems (MEMS) and microelectronics face challenges such as high cost, limited scalability, contamination risks, and incompatibility with CMOS processes due to reliance on high temperature processing and non-planar perforations, which restrict their integration and vacuum control capabilities.
Innovation Solution
The development of low-temperature, multi-layered, planar microshells with a damascene process for self-aligned perforations, integrated getter layers for contamination control, and a sealing mechanism involving a non-hermetic occluding layer and hermetic sealing layer to achieve controlled vacuum environments, allowing for integration with CMOS processes and reduced residual stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high temperature processing is used to form microshells, then sealing and encapsulation reliability is improved, but compatibility with CMOS processes deteriorates
Solution Approach 1:
The patent changes the temperature parameter from conventional high temperature (above 400°C) to low temperature (below 400°C) processing. This enables CMOS compatibility while maintaining sealing reliability through alternative low-temperature deposition and annealing processes that achieve sufficient seal integrity without damaging underlying CMOS circuits.
Solution Approach 2:
The patent replaces thermal-mechanical sealing (reliant on high temperature) with a multi-layered sealing mechanism using alternating porous and non-porous dielectric layers. The sealing is achieved through deposition processes and controlled porosity rather than high-temperature sintering, enabling integration with temperature-sensitive CMOS devices.
2Reliability
If non-planar perforations are used in microshells, then vacuum access is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the microshell structure into multiple alternating layers of porous and non-porous dielectric materials. This segmentation allows planar perforations to be formed through selective etching of porous layers, simplifying manufacturing while maintaining vacuum access through the layered architecture that provides both structural integrity and vacuum pathways.
Solution Approach 2:
The patent introduces porous dielectric layers as intermediary structures between the solid microshell and the vacuum environment. These porous layers serve as both structural components and vacuum access pathways, allowing simple planar perforations to effectively reach the vacuum cavity while the alternating layer structure provides mechanical strength.
3Device complexity
If conventional single-layer microshells are used, then device complexity is reduced, but contamination control and vacuum precision deteriorate
Solution Approach 1:
The patent segments the microshell into multiple alternating layers with different porosity characteristics. Porous layers provide contamination absorption and filtering capabilities, while non-porous layers provide hermetic sealing and structural integrity. This segmented architecture enhances contamination control and vacuum precision without requiring complex external systems.
Solution Approach 2:
The patent uses composite microshell structures combining porous and non-porous dielectric materials in alternating layers. This composite architecture provides both contamination absorption (through porous layers) and hermetic sealing (through non-porous layers), achieving superior contamination control and vacuum precision compared to single-layer structures.
4Adaptability or versatility
If planar microshells with multi-layered structure are used, then integration with CMOS and scalability are improved, but device complexity increases
Solution Approach 1:
The patent designs the multi-layered microshell structure to serve multiple functions simultaneously: structural support, contamination filtering, vacuum sealing, and thermal management. The alternating porous and non-porous layers provide hermeticity while the planar geometry enables standard CMOS fabrication processes, achieving scalability and integration without proportionally increasing complexity.
Solution Approach 2:
The patent applies different material properties (porous vs. non-porous) at different locations within the microshell structure to optimize local functions. Non-porous layers provide hermetic sealing at critical interfaces, while porous layers provide contamination absorption in exposed regions. This localized optimization enables CMOS compatibility and scalability while managing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables cost-effective, scalable, and reliable encapsulation of MEMS and microelectronics with improved vacuum control and reduced contamination, facilitating seamless integration with CMOS processes and enhancing the robustness of microshells.
Implementation Method 1
In another embodiment, the pre-sealing layer further includes a large surface area getter layer to remove contaminants from the space ultimately enclosed by the microshell
Implementation Method 2
In still another embodiment, the sealing layer includes a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation
Data Source
AI summary
Microshells for encapsulation of devices such as MEMS and microelectronics. In an embodiment, the microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation as a function of the dimension of the perforation to form cavities having different vacuum levels on the same substrate.