Microstructured CMOS Photodetectors for Thin-Chip NIR Absorption
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Solution Overview
Problem
Current CMOS image sensors face challenges in achieving higher spatial resolution with smaller chip sizes, particularly in the near-infrared region, due to weak optical absorption, which limits their external quantum efficiency and requires enhancement techniques like photon trapping to improve absorption efficiency.
Innovation Solution
The development of semiconductor devices with microstructure-enhanced absorption characteristics, featuring nanoholes and doped regions, integrated with ASICs and a dielectric base, to enhance optical absorption and quantum efficiency, particularly in the near-infrared range, by leveraging micro/nano hole structures and doped regions to trap light and increase absorption efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor thickness is decreased to achieve smaller chip size and higher spatial resolution, then chip size is reduced and spatial resolution is improved, but optical absorption efficiency decreases
Solution Approach 1:
The patent introduces micro/nano hole structures that extend vertically into the semiconductor substrate, transforming a two-dimensional surface problem into a three-dimensional light-trapping solution. These holes create multiple internal reflections and increase the effective optical path length without increasing the lateral chip dimensions, thereby maintaining small chip size while improving optical absorption efficiency in the thickness direction.
Solution Approach 2:
The patent employs porous semiconductor structures with micro/nano holes arranged in periodic or aperiodic patterns. These porous structures increase the surface area and create multiple light-trapping interfaces within the thin semiconductor layer, enabling enhanced optical absorption efficiency despite reduced material thickness, thus resolving the contradiction between small chip size and high absorption efficiency.
2Reliability
If micro/nano hole structures are introduced to enhance optical absorption, then optical absorption efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor substrate into multiple regions with micro/nano holes arranged in systematic periodic or aperiodic patterns. This segmentation approach allows the complex light-trapping function to be achieved through repeated simple structural units, making the fabrication process more manageable and the device structure more predictable, thereby reducing the practical complexity despite the enhanced optical functionality.
Solution Approach 2:
The patent optimizes key parameters such as hole diameter (10-2000 nm), depth (10-2000 nm), spacing (10-1500 nm), and arrangement patterns to achieve desired optical absorption characteristics. By systematically tuning these parameters, the patent balances the enhancement of optical absorption efficiency with the management of structural complexity, allowing for optimized performance without excessive fabrication difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the external quantum efficiency and optical absorption in CMOS image sensors, particularly in the near-infrared range, enabling higher spatial resolution and faster response times, while reducing power consumption and cost, thus addressing the limitations of existing technologies.
Implementation Method 1
micro/nano hole or holes are used for light trapping, extending thin Si operating wavelength range of 300-1050 nm and thin Ge, Ge alloy wavelength range of 300-1700 nm
Implementation Method 2
Holes in CIS can have a lateral dimension range of 10-2000 nm and in some cases 10-10000 nm and a depth range of 10-2000 nm
Implementation Method 3
Complementary metal oxide semiconductor (CMOS) image sensors (CIS) are used in many products including cameras for smartphones, tablets, laptops
Data Source
AI summary
Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.