Microvia Barrier Ring Structure for CTE Mismatch Cracking
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Solution Overview
Problem
The coefficient of thermal expansion (CTE) mismatch between metal microvias and dielectric layers in package substrates leads to stress and strain, causing microvia cracking during heat processing, which degrades signal integrity and overall device performance.
Innovation Solution
Introducing a barrier ring of CTE-matching material around the microvia, particularly at high stress locations, to distribute stress and reduce cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-core organic package substrate with microvias is used to provide interconnectivity, then device integration and signal transmission are enabled, but stress and strain are generated during heat processing due to CTE mismatch between metal microvias and dielectric layers, causing microvia cracking
Solution Approach 1:
The patent introduces a barrier ring made of CTE-matching material (such as copper or copper alloy) that is different from both the dielectric material and the microvia fill metal. This composite structure combines materials with different CTE properties: the inner barrier ring matches the microvia CTE, while the outer dielectric layer has higher CTE. This composite material approach resolves the CTE mismatch stress by creating a gradual transition zone that distributes thermal stress more evenly, preventing microvia cracking during solder reflow and temperature cycling while maintaining signal integrity.
2Ease of manufacture
If the dielectric material around the microvia is used as-is, then manufacturing simplicity is maintained, but the CTE mismatch (ΔCTE ≥ 17 ppm/°C) causes stress concentration at corner interfaces, leading to microvia cracking during solder reflow (240-250°C)
Solution Approach 1:
The patent segments the dielectric layer around the microvia by introducing a barrier ring structure that divides the homogeneous dielectric material into distinct regions: an inner barrier ring region with CTE-matching material and an outer dielectric region with organic material. This segmentation creates a functional gradient that addresses the CTE mismatch problem while maintaining manufacturing feasibility through standard PCB fabrication processes such as drilling, plating, and lamination.
Solution Approach 2:
The barrier ring acts as an intermediary material layer between the microvia fill metal and the organic dielectric material. This intermediary structure has CTE properties that match the microvia (e.g., copper CTE ≈ 17 ppm/°C) rather than the dielectric (e.g., BT-epoxy CTE ≈ 34-40 ppm/°C), creating a gradual CTE transition that reduces thermal stress concentration at the microvia-dielectric interface during solder reflow processing.
3Productivity
If temperature cycling and solder reflow processing are performed to assemble the package, then device mounting and interconnection are achieved, but the thermal stress from CTE mismatch causes microvia cracking and delamination, degrading signal integrity
Solution Approach 1:
The barrier ring is incorporated into the PCB structure before final assembly, providing preemptive stress relief capability. This pre-cushioning structure absorbs and distributes the thermal stress that will occur during subsequent solder reflow and temperature cycling operations, preventing microvia cracking and delamination before they can occur, thereby preserving signal integrity throughout the device lifecycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances microvia reliability by mitigating stress and strain, maintaining signal integrity and improving the overall performance of semiconductor devices.
Implementation Method 1
the coefficient of thermal expansion (CTE) mismatch between dissimilar materials of the metal in the microvias formed within organic dielectric layers... can cause stress and strain and eventual cracking in the dielectric material around the microvia when the in-process package is subjected to temperature cycling
Data Source
AI summary
A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.