Microwave Backhaul Clock Distribution Using TDM Sync Frames

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Solution Overview

Problem

Current methods for clock synchronization in mobile backhaul networks, such as synchronous Ethernet and IEEE 1588v2, face challenges with packet delay variation, asymmetric delays, and bandwidth consumption, particularly under high user traffic loading conditions, and are not suitable for providing phase synchronization required by 3G and 4G/LTE TDD base stations.

Innovation Solution

A system that generates a clock signal and transmits it over a radio channel network using frames with a synchronization value, allowing child nodes to perform frequency synchronization using phase-lock loops, and includes a Network Synchronization Module (NSM) for jitter attenuation and phase synchronization, enabling TDM-quality clock synchronization independent of network loading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If packet-based IEEE 1588v2 PTP protocol is used for clock synchronization, then frequency and phase synchronization can be achieved, but packet delay variation and asymmetric delays occur under high user traffic loading conditions

Engineering Contradiction:
Improvesynchronization precisionVSAvoidsynchronization reliability under traffic load
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent segments the synchronization function from user data traffic by using separate TDM channels (E1/DS1) dedicated solely to clock synchronization. This segmentation isolates the synchronization signal from packet-based user traffic, eliminating packet delay variation and asymmetric delays that affect IEEE 1588v2 under high load conditions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces TDM (Time Division Multiplexing) as an intermediary mechanism to transport clock synchronization signals. The TDM framework provides deterministic timing and fixed bandwidth allocation, acting as a mediator between the packet-based IP network and the precise clock synchronization requirements, thereby eliminating jitter and delay variation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If synchronous Ethernet is used to transport clock synchronization, then clock signal can be injected into bit stream, but every intervening node must support Synchronous Ethernet requiring expensive upgrades

Engineering Contradiction:
Improveclock synchronization operationVSAvoidnetwork node upgrade requirements
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent makes existing TDM network infrastructure multi-functional by enabling it to carry both traditional voice/data traffic and clock synchronization signals simultaneously. The E1/DS1 channels serve dual purposes: maintaining legacy TDM services while providing precise clock distribution, thereby eliminating the need for expensive synchronous Ethernet upgrades at network nodes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables the existing TDM network to self-serve the clock synchronization function without requiring external synchronization infrastructure. The TDM network's inherent timing structure and fixed bandwidth allocation allow it to naturally provide deterministic clock distribution, making external synchronous Ethernet infrastructure unnecessary.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If dedicated timing packets are transmitted within data packet stream for IEEE 1588v2, then Master-Slave synchronization relationship is maintained, but valuable bandwidth is consumed

Engineering Contradiction:
Improvephase synchronization accuracyVSAvoidbandwidth consumption
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts the clock synchronization function from the packet-based data stream and places it in separate dedicated TDM channels. By taking out the synchronization signal from the IP packet flow, the system eliminates bandwidth consumption for timing packets while maintaining precise phase synchronization through the efficient TDM transport mechanism.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution provides reliable frequency and phase synchronization without impacting radio link payload, reduces the need for expensive network upgrades, and supports phase synchronization required for 3G and 4G/LTE TDD base stations, while minimizing IP migration risks and avoiding packet delay variations.

Implementation Method 1

Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop

Methodology Applied
Scientific EffectPhase-lock loop:

Implementation Method 2

The first child node may be configured to attenuate jitter of the first frame

Methodology Applied
Scientific EffectJitter attenuation: Damping

Data Source

PatentUS9609610B2Synchronization distribution in microwave backhaul networks
Publication Date: 2017.03.28 AVIAT U S
  • US9609610B2 patent drawing
  • US9609610B2 patent drawing
  • US9609610B2 patent drawing

AI summary

In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.