Microwave Backhaul Frame Synchronization for Phase-Accurate Clock Delivery
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Solution Overview
Problem
Current methods for clock synchronization in Ethernet backhaul networks, such as synchronous Ethernet and IEEE 1588v2, face challenges like high costs, packet delay variation, and bandwidth consumption, especially when supporting 3G and 4G/LTE TDD base stations that require phase synchronization, which is not adequately addressed by traditional PDH and SDH networks.
Innovation Solution
A system that uses a clock signal to generate frames with synchronization values transmitted over a radio channel network, allowing child nodes to perform frequency synchronization using phase-lock loops, and includes a Network Synchronization Module (NSM) for jitter attenuation and phase synchronization, enabling TDM-quality clock synchronization without requiring network-wide upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous Ethernet is used to transport clock synchronization, then clock delivery is achieved, but every intervening node must support Synchronous Ethernet requiring expensive upgrades
Solution Approach 1:
The patent segments the synchronization function by separating the clock signal transport from the data payload transport. Only the root node and child nodes need synchronization capabilities, while intermediate nodes can operate with standard Ethernet equipment. This is achieved by embedding synchronization values in frame overhead rather than requiring end-to-end synchronous Ethernet infrastructure.
Solution Approach 2:
The patent introduces an intermediary mechanism where synchronization values are carried within Ethernet frame overhead structures. This allows standard Ethernet switches and routers to forward frames without needing to understand or process the synchronization information, acting as a mediator that enables synchronization over conventional Ethernet infrastructure.
2Measurement precision
If IEEE 1588v2 packet-based timing protocol is used, then frequency and phase synchronization is provided, but packet delay variation and asymmetric delays occur especially with high user traffic loading
Solution Approach 1:
The patent extracts the synchronization function from the data packet stream by placing synchronization values in the frame overhead rather than relying on dedicated timing packets within the user data stream. This separation eliminates the problem of packet delay variation affecting synchronization accuracy, as the synchronization values are transmitted in a controlled manner independent of user traffic loading conditions.
3Reliability
If dedicated timing packets are transmitted within data packet stream, then Master-Slave synchronization relationship is maintained, but valuable bandwidth is consumed
Solution Approach 1:
The patent merges the synchronization function with the existing Ethernet frame structure by utilizing the frame overhead for carrying synchronization values. This combines data transport and synchronization functions into a single frame structure, eliminating the need for separate dedicated timing packets and thereby conserving bandwidth while maintaining synchronization reliability.
4Reliability
If synchronous Ethernet is used, then end-end clock delivery is achieved, but IEEE standardized Synchronous Ethernet cannot distribute phase alignment or time of day
Solution Approach 1:
The patent changes the synchronization parameter being transported by including not only frequency information but also phase alignment values and time of day information in the synchronization data. This allows the system to provide comprehensive synchronization including phase alignment for TDD base stations, going beyond what traditional synchronous Ethernet can deliver.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides efficient and accurate frequency and phase synchronization for 3G and 4G/LTE services, reducing the need for expensive upgrades and maintaining TDM clock synchronization, while scaling to large IP backhaul access networks without packet delay variations or asymmetric delays.
Implementation Method 1
Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop
Data Source
AI summary
In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.