Microwave IC Packaging via Thin-Film Tile Ground Planes
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Solution Overview
Problem
Conventional microwave IC packaging using silicon or SOI substrates faces challenges with parasitic inductance and grounding issues, limiting high-frequency performance and automated testing capabilities due to wire-bonding and the incompatibility of flip-chip processing with customer manufacturing processes.
Innovation Solution
The integration of solder bumping and flip-chip assembly onto a thin-film tile with patterned vias and ground planes allows for flexible ground connections and automated testing, enabling effective grounding and testing of silicon-based ICs at high frequencies without the need for special handling equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire-bonding is used for grounding silicon or SOI IC dies, then the ICs can be packaged using conventional methods, but the wire-bonds have significant inductance that limits grounding effectiveness at high frequencies
Solution Approach 1:
The patent extracts the grounding function from the wire-bond structure and relocates it to the substrate level. Ground planes are formed on the substrate beneath and around the IC die, providing low-inductance ground paths that are independent of the wire-bond signal connections. This separates the grounding function from the signal interconnect function.
Solution Approach 2:
The patent transitions from one-dimensional wire-bond grounding (edges only) to two-dimensional ground plane coverage. Ground planes are extended beneath and around the die in multiple dimensions, providing ground paths from all areas of the die rather than just edge locations, thereby reducing inductance without requiring flip-chip orientation.
2Reliability
If through-hole vias are used in III-V IC dies to achieve low inductance ground connections, then automated wafer-probe testing can be implemented, but the materials are toxic and more expensive than silicon
Solution Approach 1:
The patent introduces a substrate as an intermediary structure that provides through-hole via connectivity without requiring the IC die itself to be made of III-V materials. The substrate contains the via holes and ground planes, while silicon IC dies are mounted on top and connected to the substrate's ground system through wire-bonds or other interconnects. This mediator approach enables low-inductance grounding and automated testing capabilities while maintaining compatibility with inexpensive, non-toxic silicon fabrication.
3Object-affected harmful factors
If flip-chip assembly is used to improve grounding, then low inductance ground connections can be achieved, but customer manufacturing processes cannot handle the special processing requirements
Solution Approach 1:
Instead of requiring the IC die to be flipped for optimal grounding (flip-chip), the patent inverts the approach by providing ground planes on the substrate in the conventional upright mounting orientation. Ground planes are placed beneath and around the die in its normal orientation, eliminating the need for flip-chip assembly while achieving similar low-inductance grounding performance. This allows customers to use standard wire-bonded assembly processes.
4Ease of operation
If packaged ICs are used to protect the die, then handling is simplified for customers, but the package degrades microwave performance due to bond-wire inductance
Solution Approach 1:
The patent performs grounding preparation in advance by forming extensive ground planes on the substrate before the IC die is packaged. These pre-established ground paths provide low-inductance references that remain effective even after packaging. The grounding infrastructure is built into the substrate-die assembly prior to final packaging, ensuring microwave performance is optimized before the protective package is applied.
Data Source
AI summary
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.