Mid-Gap Metal Gate Fill for Multi-Vt GAA Nanosheets
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device manufacturing, particularly for gate-all-around (GAA) devices, there is a challenge in reducing metal gate resistance while scaling down transistor sizes, which affects device performance due to high gate resistances and limited threshold voltage tuning range as device geometries shrink.
Innovation Solution
The method involves forming P-dipole and N-dipole stacks on a semiconductor substrate, followed by depositing a mid-gap fill material using atomic layer deposition to reduce gate resistance and achieve multi-threshold voltage capability, by driving metal atoms into high-κ dielectric layers and using mid-gap work function materials to adjust the effective work function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing n- or p-metal layers combined with dipole are used for gate-all-around devices, then multi-threshold voltage capability is achieved, but gate resistance becomes high which degrades device performance
Solution Approach 1:
The patent uses a composite gate structure combining a high-κ dielectric layer with a mid-gap metal layer. The high-κ dielectric (e.g., HfO2, ZrO2) provides threshold voltage tuning capability through its high dielectric constant, while the mid-gap metal layer (e.g., TiN, TaN, WN) provides low gate resistance. This composite approach achieves both multi-Vt capability and low resistance without relying on traditional dipole structures.
Solution Approach 2:
The patent adjusts the work function of the gate by changing the metal composition and thickness parameters. By selecting metals with mid-gap work functions (4.5-5.5 eV) and controlling their thickness relative to the high-κ dielectric layer, the effective gate work function can be tuned to achieve different threshold voltages while maintaining low resistance.
2Adaptability or versatility
If film thickness is scaled down further to achieve multi-Vt in advanced GAA nodes, then threshold voltage tuning range is extended, but manufacturing precision becomes difficult to maintain
Solution Approach 1:
Instead of relying solely on ultra-thin film thickness scaling (which becomes difficult to control at <4 nm), the patent uses a composite high-κ dielectric/mid-gap metal structure. The high-κ dielectric layer thickness can be controlled more precisely (e.g., 1-3 nm) while the metal layer provides additional tuning capability through composition control, achieving multi-Vt with better manufacturing precision.
3Productivity
If device geometry is shrunk to increase functional density, then chip area utilization is improved, but gate resistance increases which limits switching speeds
Solution Approach 1:
The composite gate structure with mid-gap metal layer provides inherently lower resistance compared to traditional metal gates. This allows continued device scaling and increased functional density while maintaining low gate resistance and high switching speeds, as the mid-gap metal materials (TaN, WN, TiN) have superior conductivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate resistance and enhances multi-threshold voltage capability in advanced GAA nodes, enabling improved device performance without increasing equivalent oxide thickness.
Implementation Method 1
depositing a high-κ dielectric layer on the interfacial layer
Implementation Method 2
depositing a mid-gap fill material on the exposed high-κ dielectric layer
Data Source
AI summary
Embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-Vt capability in the scaled space between nanosheets in advanced GAA nodes. One or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. In one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. After dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. If the work function was shifted in either P-dipole or N-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.