Mid-Layer Interposer for 3D Wafer Reconstitution
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Solution Overview
Problem
Traditional 3D wafer reconstitution techniques face limitations in hybrid bonded die stacking, particularly in bridging across different die boundaries, leading to topography differences, voids, non-bonding issues, and inefficiencies in pin density and latency.
Innovation Solution
The implementation of a mid-layer interposer with wafer reconstitution sequences using wafer-on-wafer or chip-on-wafer hybrid bonding techniques, facilitating high pin density, low latency, and flexible power delivery through dielectric-dielectric and metal-metal bonding, along with through vias for vertical interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 3D wafer reconstitution techniques are used for hybrid bonded die stacking, then die integration density is improved, but topography differences and voids occur leading to bonding defects
Solution Approach 1:
The patent introduces an interposer layer as an intermediary between the first and second dies. This interposer acts as a mediator that absorbs topography differences and enables uniform bonding surfaces, thereby resolving the bonding defects caused by direct die-to-die stacking while maintaining high integration density.
Solution Approach 2:
The patent segments the direct die-to-die bonding interface into two separate bonding interfaces: first die-to-interposer and interposer-to-second die. This segmentation allows each bonding interface to be independently optimized and controlled, eliminating the topography mismatch problems that occur in direct hybrid bonding.
2Productivity
If wafer-on-wafer or chip-on-wafer hybrid bonding is used, then pin density is improved, but latency increases due to complex interconnection paths
Solution Approach 1:
The patent transitions from planar 2D bonding to 3D vertical stacking with the interposer positioned between dies. This dimensional change enables higher pin density through vertical interconnection while the interposer's routing layers provide optimized signal paths that minimize latency despite the three-dimensional architecture.
3Area of stationary object
If multiple dies are stacked directly without interposer, then circuit board area is reduced, but power distribution and heat management become difficult
Solution Approach 1:
The interposer serves multiple functions simultaneously: it provides mechanical support for stacked dies, enables electrical interconnections through through-vias, facilitates power distribution through dedicated power rails, and acts as a thermal management interface. This multi-functionality allows compact 3D stacking while maintaining ease of power distribution.
Data Source
AI summary
A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. Second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. Dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.