Middle-Voltage Transistor Doping Gradient for Gate Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices integrate more elements into a given area, the shrinking feature size leads to issues such as current leakage due to the etching of the gate dielectric layer during the fabrication process.
Innovation Solution
A middle voltage transistor structure is developed, featuring a substrate with a gate and a gate dielectric layer, along with first and second lightly doping regions and a source/drain doping region. The second lightly doping region surrounds the source/drain region, and a silicide layer covers the source/drain region, extending between the edges of the lightly doping regions to prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feature size is shrunk to integrate more elements into a given area, then the integration density is improved, but current leakage occurs due to gate dielectric layer etching
Solution Approach 1:
The patent applies preliminary action by forming the lightly doped drain (LDD) regions before the gate dielectric layer is etched. This preliminary doping creates a gradual transition region that prevents direct contact between the highly doped source/drain and the gate dielectric, thereby preventing current leakage that would otherwise occur during subsequent etching processes.
Solution Approach 2:
The patent changes the doping concentration parameter by creating a gradient from the lightly doped drain regions to the heavily doped source/drain regions. This parameter change in doping concentration establishes a smooth transition that eliminates the abrupt junction causing leakage, while maintaining the scaled dimensions required for high integration density.
2Ease of manufacture
If the gate dielectric layer is etched during fabrication, then the manufacturing process is simplified, but current leakage of the transistor occurs
Solution Approach 1:
The LDD regions are formed in advance before the gate dielectric etching step. This preliminary action ensures that when the gate dielectric is subsequently etched, the lightly doped regions are already in place to prevent leakage, thus maintaining both manufacturing simplicity and device reliability.
Solution Approach 2:
The lightly doped drain regions act as an intermediary between the heavily doped source/drain and the gate dielectric layer. This intermediate doping region mediates the interaction between these structures, preventing direct harmful contact and eliminating leakage paths while allowing the gate dielectric to be etched as needed.
3Reliability
If the silicide layer extends between the edges of lightly doping regions, then current leakage is prevented, but the device complexity increases
Solution Approach 1:
The patent uses composite materials by combining silicon doping regions with metal silicide layers. The silicide layer is deposited over the source/drain regions and extends between the LDD edges, creating a composite structure that provides both low resistance contact and leakage prevention. This composite approach achieves reliability improvement without requiring fundamentally new device concepts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed transistor structure effectively prevents current leakage by creating a dopant concentration gradient through the lightly doping regions and the silicide layer, ensuring reliable operation even at reduced voltages.
Implementation Method 1
a first ion implantation process is performed by taking the mask layer as a first mask to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions
Data Source
AI summary
A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.