Mid-plane Chip Package Planar Substrate Layout
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Solution Overview
Problem
The increasing demand for thinner computer devices necessitates a reduction in the mid-plane thickness of chip packages, as conventional designs stack the die, substrate, and main logic board serially, resulting in a significant Z dimension that hinders miniaturization and heat dissipation efficiency.
Innovation Solution
The die and main logic board are coupled to the same surface of the substrate, reducing the overall thickness by eliminating the need for serial stacking, and a thermal conductive plate member is used to enhance heat dissipation by contacting the substrate's opposite surface, allowing heat to flow through the substrate and plate member for efficient cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the die, substrate, and main logic board are stacked serially in a conventional arrangement, then the structural integrity and signal transmission are maintained, but the Z dimension (thickness) increases to between 3.3 mm and 4.2 mm
Solution Approach 1:
The patent transitions from a one-dimensional vertical stacking arrangement to a two-dimensional planar arrangement where the die and main logic board are coupled to the same surface of the substrate. This dimensional change eliminates the need for serial stacking, reducing the Z dimension from 3.3-4.2 mm to approximately 2.1-2.4 mm while maintaining all necessary functional connections through lateral routing on the substrate.
2Length of stationary object
If the die and main logic board are coupled to the same surface of the substrate, then the Z dimension is reduced by at least the thickness of the main logic board, but the routing complexity on the substrate increases
Solution Approach 1:
The patent extracts the main logic board from the vertical stacking sequence and positions it laterally adjacent to the die on the same substrate surface. This extraction eliminates the need for vertical signal routing through multiple layers, replacing it with planar routing that reduces overall thickness while distributing the routing complexity across the substrate surface rather than concentrating it in vertical interconnects.
3Temperature
If conventional serial stacking is used, then heat dissipation path length increases, but the structural assembly is simpler to manufacture
Solution Approach 1:
The patent introduces lateral heat dissipation pathways by positioning the main logic board adjacent to the die on the same surface, creating multiple parallel heat conduction paths through the substrate. This two-dimensional heat dissipation architecture reduces the effective heat transfer path length compared to vertical stacking, improving thermal management while using standard substrate fabrication processes that maintain manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the chip package's Z dimension by at least the thickness of the main logic board, achieving a thinner design while improving heat transfer efficiency by up to 30% through simultaneous cooling from both sides.
Implementation Method 1
a plate member coupled to the substrate on a second surface opposing the first surface of the substrate. The plate member comprises a thermal conductive material and is in thermal contact with the second surface of the substrate in a region opposite to the first region on the first surface such that heat generated from at least one component in the at least one die flows in up into the heat dissipation system and down through the substrate and into the plate member
Data Source
AI summary
A chip package for a computer system includes a substrate having a first region and a second region on a first surface, at least one die coupled to the first region on the first surface of the substrate and a main logic board coupled to the second region on the first surface of the substrate. By coupling the die and the main logic board on the first surface of the substrate, an overall thickness of the chip package is reduced.