MIL-1553 Data Refresh Latch for Read/Write Overlap Avoidance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Asynchronous devices in communication networks experience data staleness due to clock skew, leading to read/write interval overlaps and the provision of stale data when one device's write cycle is ignored during overlap with a higher-priority read cycle.
Innovation Solution
Implementing a read/write overlap avoidance latch and delay mechanism in the device controller to prevent write operations during read cycles, using a rising edge D flip-flop and clear input to reset the latch after a delay period, ensuring data freshness by avoiding cycle overlaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous devices operate with independent clocks, then device independence and flexibility are improved, but read/write interval overlaps occur causing data staleness
Solution Approach 1:
A latch circuit is introduced as an intermediary component between the read and write operations. The latch captures the read request signal and holds it active throughout the read cycle, preventing write operations from occurring during the read interval. This mediator ensures that read and write operations do not overlap, maintaining data freshness while preserving asynchronous device independence.
2Reliability
If read cycle has higher priority during overlap, then read operation reliability is improved, but write operation is ignored resulting in stale data
Solution Approach 1:
The latch circuit performs preliminary action by capturing the read request signal before the read cycle begins and maintaining this state throughout the read interval. This preliminary latching action proactively prevents write operations from being initiated during the read cycle, eliminating the overlap problem before it can cause stale data to be written.
3Reliability
If devices are synchronized in master/slave relationship, then clock skew is reduced, but system complexity and dependency increase
Solution Approach 1:
The synchronization problem is extracted and isolated to a specific component (the latch circuit) that handles only the timing coordination of read/write operations. The majority of the system remains asynchronous with independent clocks, maintaining simplicity and flexibility. Only the critical read/write timing interface requires synchronization through the latch, rather than synchronizing the entire system.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An asynchronous communication system configured to operate a MIL-1553 protocol. The system includes: a bus (102); a bus controller (104) coupled to the bus (102) that is configured to control access to the bus (102); a remote terminal (106) connected to the bus (102); a device controller (108) connected to the remote terminal (106); and a read/write overlap avoidance latch (280) connected to the remote terminal (106). The read/write overlap avoidance latch (280) provides an active signal (270, 282) to the device controller (108) that prevents the device controller (108) from writing data to the remote terminal (106) while the bus controller (104) is reading data from the device controller (108) during a read cycle.