Miller Capacitance Tolerant Buffer for Clock Tree Timing
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Solution Overview
Problem
The Miller Effect causes unpredictable timing mismatches in digital system designs due to variations in output load and input signal transition time, leading to increased power consumption and potential hold time failures, especially in deep sub-micron designs.
Innovation Solution
A Miller capacitance tolerant buffer element is designed, comprising a source follower module with a gain less than or equal to unity and a pull-up/pull-down module, which reduces the impact of Miller capacitance by ensuring the output signal follows the input signal with a predetermined delay independent of Miller capacitance, thus stabilizing clock tree performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If standard library cells with small number of transistor stages are used in clock distribution trees, then device complexity is reduced, but Miller Effect becomes more dominant causing timing mismatches
Solution Approach 1:
The patent changes the voltage gain parameter of the buffer cell to be less than unity (typically 0.5 to 0.9), which fundamentally alters the Miller Effect behavior. By using a source follower configuration instead of a standard inverter, the gain reduction eliminates the capacitance multiplication effect while maintaining buffering functionality, thus resolving the timing accuracy issue without increasing device complexity
2Reliability
If larger drive cells are used to compensate for Miller Effect during logic synthesis, then timing mismatches are avoided, but power consumption increases
Solution Approach 1:
Instead of increasing cell size to compensate for Miller Effect, the patent changes the operational parameter (voltage gain) of the buffer cell to be less than unity. This parameter change eliminates the root cause of timing mismatches without requiring larger transistors, thereby avoiding the associated increase in power consumption while maintaining timing accuracy
3Quantity of substance
If Miller capacitance is reflected back to preceding stage driver, then input capacitance variation occurs, but this variation causes unpredictable timing mismatches between logic synthesis and post-layout phases
Solution Approach 1:
The patent changes the voltage gain parameter to less than unity, which fundamentally alters the Miller capacitance reflection behavior. With gain < 1, the Miller capacitance formula C_in = C_gd(1-A) produces a reduced and predictable input capacitance that does not vary unpredictably with load changes, thereby improving timing predictability between design phases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in predictable performance, reduced power consumption, and faster timing convergence, as demonstrated by simulations showing lower current consumption and comparable signal delays compared to conventional buffers.
Implementation Method 1
The input capacitance due to the overlap capacitance between the gate and drain of the transistor is partially reflected back to an output of preceding stage driver. The gate-drain overlap capacitance of a MOSFET transistor is multiplied by gain and reflected at gate because of Miller Effect and known as the Miller Capacitance.
Data Source
AI summary
A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.